iverilog

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 Here is the example behavioral Verilog code in question module constant; reg [7:0] foo; initial begin foo = 1'bz; $display("%H", foo); end endmodule Icarus Verilog gave me $ iverilog -o constant constant.v $ ./constant 0Z However, according to this website (and the lecturer of an FPGA course I am taking), If number is smaller than the size constant, then it will be padded to the left with zeros. If the most significant bit of a specified number has an unknown (x) or high-impedance (z) value,

问题 I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code: module up_down_4bitcounter ( out, up_down, clk, data, reset ); //Output Ports output [3:0] out; //Input Ports input [3:0] data; input up_down, clk, reset; //Internal Variables reg [3:0] out; //Start of Code always @(negedge clk) if (reset) begin // active high reset out <= 4'b0 ; end else if (up_down) begin out <= out +

问题 I'm new to Verilog and would really appreciate it if someone could help me with this. I have a task written in a separate file - "task.v" : module task_create(); task assign_inp; reg a,b,c,d; //details endtask endmodule I have a module that is calling this task: module tb(); `include "task.v" assign_inp(a,b,c,d); endmodule When I execute this, I get this error: Module definition task_create cannot nest into module tb When I remove the module and endmodule in task.v, I get this error: Task