问题
I have some tasks in verilog file. And I want to see them in simvision when they are triggered.
Is there any way to find task's triggered point in simvision?
Is this can not be able to visualize in simvision? I know that manner like using print or display statements. But I need to visualize to simvision. Does anyone know that way?
UPDATE
Use a breakpoint
If you don't have access to the source of the task, or cannot modify it, >you could set a breakpoint when the task is called, execute some TCL >commands, then continue the simulation. The TCL commands could toggle a >signal or increment a counter. This could be automated with a small TCL >script. Depending on your situation, this could cause a performance hit on >the simulation time.
I want to know more this manner, would you let me know this way how to make it? Please let me know even if simple I am OK.
回答1:
I don't think there is a native way to do this, but you should check the documentation that Cadence provides. That said, there are a few options you could employ to get information into the waveform.
Add a counter
If you can modify the source for the task, you can add a global counter somewhere which increments each time the task is called. Then add the counter register to the waveform.
Toggle a bit
Similarly, you could use a single bit and toggle it when the task is called. Using a counter has the advantage that if the task can be called twice in the same time step, you will see the counter increment by 2, whereas the single bit would toggle twice and not be visible in the waveform, unless you have zero-time event capturing enabled.
Use a breakpoint
If you don't have access to the source of the task, or cannot modify it, you could set a breakpoint when the task is called, execute some TCL commands, then continue the simulation. The TCL commands could toggle a signal or increment a counter. This could be automated with a small TCL script. Depending on your situation, this could cause a performance hit on the simulation time.
来源：https://stackoverflow.com/questions/32519440/how-to-prove-a-task-in-verilog