verilog

问题 module controle(clock, reset, funct, opcode, overflow, PCW, PCCondW, PCDataW, PCSrc, EPCW, AluOutW, MemRegW, AluOp, AluSrcA, AluSrcB, BShift, BSrc, ShamtSrc, AW, RegW, RegDst, RegSrc, Loads, Stores, IRW, MemW, IorD, LSE); input [5:0] opcode, funct; input overflow, clock; output reg AW, IRW, MemW, MemRegW, EPCW, AluOutW, PCW, PCCondW, AluSrcA, BSrc, RegW, LSE, reset; output reg [2:0] BShift, PCDataW, Loads, PCSrc, RegSrc; output reg [1:0] ALuSrcB, Stores, AluOp, ShamtSrc, IorD, RegDst;

问题 I want to create an array in Verilog which is going to contain the values x , y of a given function. So each content of the array is going to contain a value of x and a value of y . So lets say that I have the following values for (x,y) (3,2) (5,10) (1,5) The final array will look something like this: Table[i][x][y] Table[0][3][2] Table[1][5][10] Table[2][1][5] Is it possible to make this array in Verilog and be synthesizable? If so, how can I access each point on this array? 回答1: I think

问题 I want to create an array in Verilog which is going to contain the values x , y of a given function. So each content of the array is going to contain a value of x and a value of y . So lets say that I have the following values for (x,y) (3,2) (5,10) (1,5) The final array will look something like this: Table[i][x][y] Table[0][3][2] Table[1][5][10] Table[2][1][5] Is it possible to make this array in Verilog and be synthesizable? If so, how can I access each point on this array? 回答1: I think

问题 I keep getting the error everytime i try to compile i'm not sure why. Can anyone help? I'm new to verilog. module D_FF(Clk, D, Reset_n, Q); input D, Clk, Reset_n; output Q; reg Q; lab4_GDL f1(.Clk(~Clk), .D(D), .Q(Qm)); lab4_GDL f2(.Clk(Clk), .D(Qm), .Q(Q)); always @(posedge Clk, negedge Reset_n) begin if (Reset_n == 0) Q <= 0; else Q <= D; end endmodule EDIT: This is what the problem was asking us to do: In this part, you will implement a memory / register circuit on the AlteraDE2 board. The

问题 I am designing an FSM in SystemVerilog for synthesis through the QuartusII (14.1) tool to put on an Altera FPGA. I am using an enum declaration to make the code much more reasonable: typedef enum logic [7:0] { CMD_INIT, CMD_WAIT, CMD_DECODE, CMD_ILLEGAL, CMD_CMD0, ... } cmd_st; ... cmd_st cs, ncs; ... Whenever Quartus synthesized this state machine, it seems to create a one-hot encoding despite the logic [7:0] part of the type. As in, when I got to add the states to SignalTap, I get all of

问题 I am developing a SystemVerilog monitor that extends ovm_monitor and I'd like to know how to import the ovm macros that I am using. I am using: `ovm_component_utils_begin `ovm_field_string `ovm_component_utils_end I tried the following at the top of my file, both of which do not compile: import ovm_pkg::ovm_monitor; import ovm_pkg::ovm_macros; and import ovm_pkg::ovm_monitor; `include "ovm_macros.svh" VCS compile error: Error-[SE] Syntax error Following verilog source has syntax error : "my

问题 In verilog I have an array of binary values. How do I take the absolute value of the subtracted values ? Verilog code: module aaa(clk); input clk; reg [7:0] a [1:9]; reg [7:0] s [1:9]; always@(posedge clk) begin s[1] = a[1] - a[2]; s[2] = a[2] - a[3]; s[3] = a[1] + a[3]; end endmodule I want my s[1] and s[2] values to be always positive . How can I do it in synthesisable verilog? I have tried using signed reg , but it shows an error. 回答1: Regardless of whether the number is signed or not twos

问题 I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it shows the result of 17/2 as 9. What should I do? Is there anyway to define something like a: output real reg [11:0] output_value ? Or is it something that has to be done by simulator settings? Simulation only (no synthesis). Example: x defined as a signed input and output_value defined as output reg. output_value = ((x >>> 1) + x) + 5; If x=+1 then output value has to be: 13/2=6

问题 I am trying to implement a simple event based Verilog simulator in Python, but I actually struggle to find some details in the specification (section 11 of IEEE 1364-2005). Let's say I just perfomed an update event on clk which now obtained the new value 1 (0 before). According to the specification this requires me to schedule 'evaluation events' for sensitive processes. Do I have to schedule the evaluation of an always @(posedge clk) block as active or inactive event? I'm guessing that the

问题 Here i have a shifter but as of rite now it only works for up to 3 bits. I've been looking and i can't find out how to make it work for up to 8 bits. module shifter(a,b,out); input [7:0] a, b; output [7:0] out; wire [7:0] out1, out2, out3; mux_8b_2to1 first(a[7:0], {a[3:0],a[7:4]}, b[2], out1); mux_8b_2to1 second(out1[7:0], {out1[5:0],out1[7:6]}, b[1], out2); mux_8b_2to1 third(out2[7:0], {out2[6:0],out2[7]}, b[0], out); endmodule 回答1: What you have is a Barrel Shifter. Two ways to make it