verilog

问题 I have a quick question. How can I use the outputs of two other modules with a new module? Example: module test1(ans, X, Y) output ans; input X, Y; do stuff endmodule module test2(ans2, X, Y) output ans2; input X, Y; do stuff endmodule module result(final_ans, ans, ans2) <------- this is what I mean. do stuff endmodule How would I go about this? How do I call the other two modules? Thank you for the help. 回答1: You do not call modules. You instance modules. Verilog is not like normal

问题 I have a quick question. How can I use the outputs of two other modules with a new module? Example: module test1(ans, X, Y) output ans; input X, Y; do stuff endmodule module test2(ans2, X, Y) output ans2; input X, Y; do stuff endmodule module result(final_ans, ans, ans2) <------- this is what I mean. do stuff endmodule How would I go about this? How do I call the other two modules? Thank you for the help. 回答1: You do not call modules. You instance modules. Verilog is not like normal

问题 Sorting five integers using bitwise or comparison operators can be achieved by first getting the highest number then the second highest then the third and so on. Here is my code in getting the highest number: #include <stdio.h> int main() { int a, b, c, d, e; int aa, bb, cc, dd, ee; a = 4; b = 2; c = 5; d = 1; e = 3; aa = (a > b) ? ((a > c) ? ((a > d) ? ((a > e) ? a : e) : ((d > e) ? d : e)) : ((c > d) ? ((c > e) ? c : e) : ((d > e) ? d : e))) : ((b > c) ? ((b > d) ? ((b > e) ? b : e) : ((d >

问题 I am trying to write a simple module to output a 14-bit number based on the value of four input signals. My attempt is shown below. module select_size( input a, input b, input c, input d, output [13:0] size ); if (a) begin assign size = 14'h2222; end else begin if (b) begin assign size = 14'h1111; end else begin if (c) begin assign size = 14'h0777; end else begin assign size = 14'h0333; end end end endmodule Upon compilation, I receive the following error: ERROR:HDLCompiler:44 - Line 67: c is

问题 Now, I'm trying to make a coarse random signal not fine. So I'm using the $urandom command in the verilog. But still I can't get the coarse random signal. the below is the my random verilog code but I don't know how to get the a coarse random signal not fine. always@(clk) begin temp = $urandom; end EDIT coarse random signal means I can tell you by using adder signal. reg [29:0] temp; always@(posedge clk or negedge rst) begin if(!rst) temp <= 0; else temp <= temp + 1; end From here, we can see

问题 I am programming with Xilinx's vivado in verilog. I was wondering why for some outputs we use reg For example reg [3:0] encoder_output we use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we use reg whenever we need to "STORE SOMETHING" Is my idea right?? 回答1: It's not actually a stupid question, despite all the downvotes. In The Beginning, The Designer created nets and registers. Nets were intended as connections between hardware elements, and had values driven

问题 I want to design a simple multiplier with the generate construct and two dimensional memory. But I can not compile the following verilog code. Could anyone give some hint please? module classic_multiplier( a, b, a_by_b); parameter M = 2; input [M-1:0] a, b; output reg [M-1:0] a_by_b [0:2*M-2]; //the first and genvar i, k; generate begin for(k = 0; k <= M-1; k=k+1) begin for(i = 0; i <= k; i=i+1) begin a_by_b[k][i] = a[i] & b[k-i]; end end end endgenerate endmodule 回答1: It seems the problem

问题 I am attempting to generate a programming file useing ISE 14.7 for some of the benchmarks provided on Trust-Hub.org. I am working with AES-T100 which contains a series verilog files. I have never worked with verilog and haven't touched VHDL in years. In theory the verilog code provided by trust-hub should work however trying it gives the compile error ERROR:HDLCompilers:27 - "../../../../../../AES-T100/src/TjIn/TSC.v" line 28 Illegal redeclaration of 'load' Now, this error is fairly self

问题 I am attempting to generate a programming file useing ISE 14.7 for some of the benchmarks provided on Trust-Hub.org. I am working with AES-T100 which contains a series verilog files. I have never worked with verilog and haven't touched VHDL in years. In theory the verilog code provided by trust-hub should work however trying it gives the compile error ERROR:HDLCompilers:27 - "../../../../../../AES-T100/src/TjIn/TSC.v" line 28 Illegal redeclaration of 'load' Now, this error is fairly self

问题 I am working towards the implementation of a channel decoder on an FPGA. Esentially , the problem sums up to this : 1) I have a matrix . I do some computations on the rows. Then, I do some computations on the columns. The decoder basically picks up each row of the matrix, performs some operations and move onto the next row. It does the same with the columns. The decoder however operates on a 1023 * 1023 matrix i.e I have 1023 rows and 1023 columns. Small test case that works : I first created