verilog

问题 I'm trying to pass an interface to a module which is an array of interfaces. interface front_port #(parameter DATA_WIDTH = 4); logic [DATA_WIDTH - 1 : 0] data; logic acknowledge; modport f_interface(input data, output acknowledge); endinterface interface front_interface #(parameter NO_OF_IN_PORTS = 3); front_port front_ports[NO_OF_IN_PORTS](); endinterface module A #(parameter NO_OF_IN_PORTS = 3) ( interface front_port; ); module testbench; font_interface #(.NO_OF_IN_PORTS(3)) my_front

问题 In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog? 回答1: There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource. Also

问题 In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog? 回答1: There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource. Also

问题 In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog? 回答1: There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource. Also

问题 I want to generate delay using counter, actually here I use counter to generate delay after each 1 Bit transfer, so that its better understand externally on fpga pin from which by SPI(serial) LCD is connected with it. Therefore I had created a shift register which shift 1 bit then gives delay then next bit(Bit-Delay-bit-delay..). Here is my code of counter: module spidelay( input wire clk, input wire enb, output reg sclkout ); reg [23:0] stmp; always @(posedge clk) begin if ( enb == 1 ) begin

问题 I started Verilog a few weeks ago and now I'm implementing MIPS pipelining on an FPGA board and I'm on the MEM part of the pipelining stage. I'm trying to code the Data memory unit (in picture -> Data memory Unit). I don't understand the use of memread. I understand that if memwrite is 1, the contents of the current address is passed to read data. So far, this is my code: module data_memory ( input wire [31:0] addr, // Memory Address input wire [31:0] write_data, // Memory Address Contents

问题 I started Verilog a few weeks ago and now I'm implementing MIPS pipelining on an FPGA board and I'm on the MEM part of the pipelining stage. I'm trying to code the Data memory unit (in picture -> Data memory Unit). I don't understand the use of memread. I understand that if memwrite is 1, the contents of the current address is passed to read data. So far, this is my code: module data_memory ( input wire [31:0] addr, // Memory Address input wire [31:0] write_data, // Memory Address Contents

问题 I came across priority encoder design and found out a new way to do it using a case statement. The only thing that is confusing is, does a case statement give priority to cases? Example: case(1'b1) A[3]: Y<=4'b1000; A[2]: Y<=4'b0100; A[1]: Y<=4'b0010; A[0]: Y<=4'b0001; default:Y<=4'b0000; endcase Here if I give A as 1111 Y gets 1000 i.e it gives priority to the first case statement. Why is this so? 回答1: Yes, there is a priority, based off of the order. According to the Verilog-2001 spec,

问题 Where Can I find algorithm details for holistic word recognition? I need to build a simple OCR system in hardware (FPGAs actually), and the scientific journals seems so abstract? Are there any open source (open core) codes for holistic word recognition? Thanks 回答1: For an algorithm that is quite suitable for FPGA implementation (embarrassingly parallel) you might look at: http://en.wikipedia.org/wiki/Cross-correlation It is fast, and easily implemented. The only thing is: it recognizes a

问题 Where Can I find algorithm details for holistic word recognition? I need to build a simple OCR system in hardware (FPGAs actually), and the scientific journals seems so abstract? Are there any open source (open core) codes for holistic word recognition? Thanks 回答1: For an algorithm that is quite suitable for FPGA implementation (embarrassingly parallel) you might look at: http://en.wikipedia.org/wiki/Cross-correlation It is fast, and easily implemented. The only thing is: it recognizes a