verilog

问题 So, I have a reg[7:0] corr_Output[0:63]; which is filled with values in my module. How I can find maximum number in this array at one CLK cycle? I wrote a 8 bit comparator: module Comparator2D( input [7:0] X1, input [7:0] indexX1, input [7:0] X2, input [7:0] indexX2, output [7:0] Y, output [7:0] indexY ); always begin if (X1 > X2) begin Y = X1; indexY = indexX1; end else begin Y = X2; indexY = indexX2; end end endmodule But I dont know how I should instantiate this module in my top design? I

问题 My code for a reaction tester works perfectly and as it should in simulation. But when I move it to my FPGA device it just stalls as soon as I press the start button and I cannot figure out what goes wrong as it is working perfectly in simulation. The concept is, when reset is pressed display Hi on the screen, when start is pressed, pick a random value from LFSR and count up to max value, thus making it a random delay. When max count for this reg is reached turn on the led, start the timer

问题 As you all might know that the MIPS instruction set supports clz (count leading zero) as follows: clz $t0,$t1 count leading zeros t0 = # of leading zeros in t1 I am writing a single cycle datapath in verilog and was just wondering what the ALU needs to support in order for me to do this... any ideas?? 回答1: Here's a possible approach (I'm ignoring the case of an input of 0, which is probably best treated as a special case): The number of leading zeros in a 32-bit number is either: the number

问题 How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again. For example 0.3545 = 2^-2 + 2^-4 + ... I have question about another way, like this. I don't know where does the minus (-) comes from: 0.46194 = 2^-1 - 2^-5 - 2^-7 + 2^-10. I have just look this from someone. but as you way, that is represented like this 0.46194 = 2^-2 + 2^-3 + 2^-4

问题 my code looks as below reg [7:0] c[1:1000]; @(posedge clk) begin g=fopen(aa.txt,"w"); for(i=0;i<1000;i=i+1) begin $fdisplay(g,"%b",c[i]); end $fclose(g); but this code is not synthesizable.i neeed a synthesizable code. I am using a vertex 6 kit 回答1: To accomplish this task (save the contents of a 1000 byte array to a file in some storage media) you only choice is to instantiate some kind of processor (like a MicroBlaze for example) in your design, and interface it to whatever media your FPGA

问题 is there a way to multiply a register/ wire with a value? e.g. ... input wire [13:0] setpoint ... if (timer>(setpoint*0.95)) 回答1: Yes this is possible, but multipliers can be quite large so use with caution. In this case the multiplicand is fixed so it will reduce the logic down quite a lot. In RTL a real (as in 0.95) does not have much meaning you need to multiply by a fixed point number, which will also limit the precision which you can represent 0.95. Allowing 10 binary places, a scaling

问题 Can anyone tell me how to write a verilog code for DWT of an image and download in to fpga. Actually my project is to write a verilog code to perform discrete wavelet transform of a medical image, can anyone frame the logic or if have the code can you send me, please I am using xilinx virtex 2 pro.. 回答1: This one is in VHDL instead of Verilog, but might still provide at least some inspiration. 回答2: Generally FPGA's come with software for programming them. Depending on manufacturer those

问题 I have the following code but I don’t know what the 3'bzzz stands for: `timescale 1ns / 1ps module reg_tercer_estado(entrada,hab,salida); input [2:0] entrada; input hab; output [2:0] salida; reg [2:0] auxsalida; always @(entrada) begin case (hab) 1'b0: auxsalida=entrada; 1'b1: auxsalida=3'bzzz; endcase end assign salida=auxsalida; endmodule 回答1: According to “HDL Compiler for Verilog” manual, 3'bzzz is 3-bit number, and z is a condition for 'disconnected' or 'high impedance' , and it's also

问题 i have a module parameter that is an array of a predefined struct. I set the default size of this array as 1 element. The idea is to override it with the appropriate size at the time of instantiation. The way i show below doesn't override the size. It only overides the first value. I can see why it would do this as the size field is not parameterized. Is there a better way than to pass a parameter for the size? Thank you for the help. module reg_slave #(parameter reg_pkg::defval_pair [0:0]

问题 is there a way to synthesize an architecture in verilog such that a deeply nested endpoint can access some top level pins (from a .ucf) without expressly routing the pins through every module of the hierarchy. In my case i have a PCIe block with a deeply nested endpoint. AT the endpoint there have an address decoder that needs to provide some signal information from pins at the top level. I'd rather not modify every intervening module to carry the necessary wires. my web searches are