verilog

问题 I am trying to code a controller/data-path implementation in Verilog, and I am confused on what will cause an unwanted latch. Essentially, I have a state machine updating on the negedge clock. This state machine sends 5 control signals (loadSquare, loadDelta, addDelta, etc.) to the data-path based on what state the machine is in. The code for the data-path and controller is shown below. Data-path //Control lines reg addSquare, addDelta, decDelta; reg loadSquare, loadDelta; //Input lines reg

问题 I am new to Verilog and I had been asked the following question: Consider a = reg[3:0] , then what values can a have so if(a) will return true ? I have no idea where to start, tried to compile some examples but all failed syntax problem . 回答1: Writing if (a) is the same as writing if (a !=0) . Since a is a 4-bit variable, you can expand that out to if (a[0] != 0 | a[1] ! = 0 | a[2] != 0 | a[3] !=0) . So a 1 in any bit position makes the expression true. Note that an unknown value x or z as an

问题 Simple question If I need to use 4 8-bit numbers, I would declare the following reg. reg [7:0] numbers [3:0] I'm quite confused about the difference between the first and second declaration ([7:0] and [3:0]). In what order should they come? Does first one stay for the size of a number while the second is for the number of numbers or vice versa? And is [7:0] or [0:7] give the right order? Thanks in advance. EDIT: Ordinary arrays of numbers look like this, for example 0000 0110 0001 There are

问题 Simple question If I need to use 4 8-bit numbers, I would declare the following reg. reg [7:0] numbers [3:0] I'm quite confused about the difference between the first and second declaration ([7:0] and [3:0]). In what order should they come? Does first one stay for the size of a number while the second is for the number of numbers or vice versa? And is [7:0] or [0:7] give the right order? Thanks in advance. EDIT: Ordinary arrays of numbers look like this, for example 0000 0110 0001 There are

问题 I am writing a Verilog code for synthesis of an algorithm, I am a little confused on what cases might cause latches to be inferred. Below is one such section of the code, though it works fine in simulation, I am worried it might cause problems on hardware. always@(b1 or b2) ..... // b1_map,b2_map,m1_map & m2_map are derived from combinational functions using b1 & b2 ..... if(b1_map<=20 && m2_map<=20 && b1_map>=0 && m2_map>=0) begin accumulator1[b1_map][m2_map]= accumulator1[b1_map][m2_map] +

问题 I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies. Which of these methods is the best way to parametrize modules? What is the difference? Is it vendor-dependent (Altera vs Xilinx)? The first method: Module definition: module busSlave #(parameter DATA_WIDTH = 1) ( input [DATA_WIDTH-1:0]

问题 Imagine we want to describe a combinational circuit that satisfy the following truth table: a b | s0 s1 s2 s3 ----------------- 0 0 | 1 d d d 0 1 | 0 1 d d 1 0 | 0 0 1 d 1 1 | 0 0 0 1 (where d stands for "don't care" value, that is, we don't care if the value of this output is 0 or 1) If we go through traditional design, we can take advantage of these "don't cares" and assign to them the most convenient values so the resulting equations (and hence, the circuit) are the most simple ones. For

问题 In class the professor said that students shouldn't say that they learned to program in Verilog. He said something like Verilog isn't used to program it's used to design. So how is Verilog different from other programming languages? 回答1: Verilog is a hardware definition language. Programming languages are generally understood to be languages for telling existing hardware what to do, not for reconfiguring said hardware. 回答2: Verilog, just like VHDL, is meant to describe hardware. Instead,

问题 I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2 and learning the ins and outs. I am trying to make a counter which is turned on and off by a switch. So far the counter counts and resets based on a key press. This is my error: Error (10119): Verilog HDL Loop Statement error at my_first_counter_enable.v(19): loop with non-constant loop condition must terminate within

问题 I am confused between these three functions and I was wondering for some explanation. If I set the range how do I make the range exclusive or inclusive? Are the ranges inclusive or exclusive if I don't specify the range? 回答1: In addition to the answer from @dave_59, there are other important differences: i) $random returns a signed 32-bit integer; $urandom and $urandom_range return unsigned 32-bit integers. ii) The random number generator for $random is specified in IEEE Std 1800-2012. With