when if(a) will return true in Verilog

扶醉桌前 提交于 2020-01-03 06:41:42

问题


I am new to Verilog and I had been asked the following question:

Consider a = reg[3:0], then what values can a have so if(a) will return true? I have no idea where to start, tried to compile some examples but all failed syntax problem.


回答1:


Writing if (a) is the same as writing if (a !=0). Since a is a 4-bit variable, you can expand that out to if (a[0] != 0 | a[1] ! = 0 | a[2] != 0 | a[3] !=0). So a 1 in any bit position makes the expression true. Note that an unknown value x or z as an operand with the equality/inequality operators results in an unknown and is considered false. But an unknown or'ed with true is true.




回答2:


reg is a verilog keyword used to declare variable types, and the expression you provided is an illegal verilog expression. You can declare a to be a 4-bit reg as the following:

reg[3:0] a;

the above makes a a 4-bit vector. Now, verilog bits might have 4 states: 0, 1, x, and z. So, any one of 4 bits of a can be in any of those states. Now you have 256 possible combinations. If you ignore x and z states, you can get 16 combinations expressed in decimals as 0 to 15.

true means that at least one bit in a is 1. In all other cases it will be false.



来源:https://stackoverflow.com/questions/50205430/when-ifa-will-return-true-in-verilog

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