verilog

问题 This is a follow-on question from How can I iteratively create buses of parameterized size to connect modules also iteratively created?. The answer is too complex to answer in a comment and the solution may be helpful for other SOs. This question is following the self-answer format. Addition answer are encouraged. The following code works and uses a bi-directional array. module Multiplier #(parameter M = 4, parameter N = 4)( input [M-1:0] A, //Input A, size M input [N-1:0] B, //Input B, size

问题 What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed to use wire in a verilog module. I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of procedural assignment statements must be of reg data type." What are procedural assignment statements? I have throughly googled this but was not able to find a clear explanation. 回答1: Wire:- Wires are used

问题 What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed to use wire in a verilog module. I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of procedural assignment statements must be of reg data type." What are procedural assignment statements? I have throughly googled this but was not able to find a clear explanation. 回答1: Wire:- Wires are used

问题 I am having a hard time understanding the following syntax in verilog: input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result = {{16{a[15]}}, {a[15:0]}}; I know the assign statement will wire something up to the result bus using wires and combinational logic, but what's up with the curly braces and 16{a[15]}? 回答1: The curly braces mean concatenation, from most significant bit (MSB) on the left down to the least significant bit (LSB) on the right. You are creating

问题 I am new to veriloghdl and I am getting this error in verilog hdl Error (10170): Verilog HDL syntax error at TrafficLight.v(59) near text "endcase"; expecting "end" Can anyone tell me what is wrong? my code is module TrafficLight(t, state, next_state, clk, out); input t, clk; output out; localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101; reg[2:0] state, next_state, tt; always@(posedge clk) begin case(state) 3'b000: if(tt < 5) next_state = s0; else begin next_state =

问题 I have some questions about reg initialization. Can I put Initial blocks in the design? Is that a good way? How to initial regs in my bottom design? Do I need to create ports in each level and give initial value from top to bottom? For each simulation, initial values are different. 回答1: Point 1: We recently had a discussion about initial statements on the Electronics forum. Initial statements in test benches are normal. In fact without initial statements it becomes a lot more difficult to

问题 i can't understand the two lines at the end of this code input [15:0] offset ; output [31:0] pc; output [31:0] pc_plus_4; reg [31:0] pc; wire [31:0] pcinc ; assign pcinc = pc +4 ; assign pc_plus_4 = {pc[31],pcinc}; assign branch_aadr = {0,pcinc + {{13{offset[15]}},offset[15:0],2'b00}}; 回答1: If you are unfamiliar with curly braces {} , they are concatenation operators. You can read about them in the IEEE Std for Verilog (for example, 1800-2009, Section 11.4.12). assign pc_plus_4 = {pc[31]

问题 I'm using mailbox in a UVM SV test bench and facing some issue while trying to write in mailbox. My code looks like bellow: class my_seqyuence extends uvm_sequence; mailbox data; some_user_defined_type mydata; function new(string name = "my_sequence"); super.new(name); data=new(); endfunction task body(); forever begin // blocking-get. program is blocked here... not why get is not returning...! data.get(mydata); decode_mydata_and_do_something_here; end endtask function void writetrans(some

问题 I'm checking primality of a number in a form of 6n+1 or 6n-1. I have the below code, but it doesn't seem to be generated correct result. module prime(clk, rst, start, A, ready, P); input clk, rst, start; input [7:0] A; output ready, P; reg ready, P; reg [7:0] divisor; reg val; always @ (posedge clk or negedge rst) begin if (!rst) begin P <= 1'bx; end else if (start) begin case (A) -1 : P <= 1; 0 : P <= 1; 1 : P <= 1; 2 : P <= 1; 3 : P <= 1; 5 : P <= 1; endcase if (A%2 == 0 && A != 2) begin P

问题 I am doing the calculation where the output is one of the next input. However the mux output just providing X and causes all the rest calculation to go wrong. How to overcome this issue? Is it due to the clock? Here is my code: module all2(input sel,clk, input signed [15:0]x,d, output signed [15:0]w,e,y); localparam u = 16'd2; wire [15:0]w1; reg [15:0]y1,e1,u1,wk; assign w = wk; assign e = e1; assign y = y1; assign w1 = (sel)?wk:16'd0; always @(posedge clk or negedge clk) y1 <= x * w1; always