Error (10170): Verilog HDL syntax error at TrafficLight.v(59) near text “endcase”; expecting “end”

问题

I am new to veriloghdl and I am getting this error in verilog hdl

Error (10170): Verilog HDL syntax error at TrafficLight.v(59) near text "endcase";  expecting "end"

Can anyone tell me what is wrong?

my code is

module TrafficLight(t, state, next_state, clk, out);

input t, clk;
output out;
localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
reg[2:0] state, next_state, tt;
always@(posedge clk)
    begin
    case(state)
        3'b000:
            if(tt < 5)
                next_state = s0;
            else
                begin
                next_state = s1;
                assign out [5:0] = 6'b100001;
                end
        3'b001:
            if(tt < 1)
                next_state = s1;
            else
            begin
                next_state = s2;
                assign out [5:0] = 6'b010001;
            end
        3'b010:
            if(tt < 1)
                next_state = s2;
            else
            begin
                next_state = s3;
                assign out [5:0] = 6'b001001;
            end
        3'b011:
            if(tt < 5)
                next_state = s3;
            else
            begin
                next_state = s4;
                assign out [5:0] = 6'b001100;
            end
        3'b100:
            if(tt < 1)
                next_state = s4;
            else
            begin
                next_state = s5;
                assign out [5:0] = 6'b001010;
            end
        3'b101:
            if(tt < 1)
                next_state = s0;
            else
                begin
                next_state = s5;
                assign out [5:0] = 6'b001001;
                end
    endcase


    always@(posedge clk);
        begin
        state = next_state;
        tt = tt - 1;
        end

endmodule

The error occured I think on the lines endcase and endmodule. I think I would have to close them with something.

回答1:

There are a couple of errors in your code -

You missed the "end" after the "endcase" statement. The end is required for the begin block just before the case statement.

You have added ";" in the always block declaration.

always@(posedge clk);
    begin
    state = next_state;
    tt = tt - 1;
    end

There is no need of an ";" in the always block.

module TrafficLight(t, state, next_state, clk, out);

input t, clk;
output out;
localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
reg[2:0] state, next_state, tt;

In the above snippet I see that you have added "state" and "next_state" as ports to the module but haven't assigned any direction to them. Either remove them as ports or make them as "input" or "output".

You would also need to remove the "assign" statement when driving the out reg. Since it is inside a procedural block you don't need an "assign" here.

You can find all the updates to your code here

来源：https://stackoverflow.com/questions/44437405/error-10170-verilog-hdl-syntax-error-at-trafficlight-v59-near-text-endcase

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verilog