verilog

问题 I am writing a Verilog code for calculating the number of digits in a decimal number. In the code below I have initialised the value of c to be equal to a. I was able to get the simulation results correctly but unable to syntesise and the error is due to 'c=a'. How can I get rid of the error ? Is there any other logic to calculate the number of digits ? Error: [Synth 8-3380] loop condition does not converge after 2000 iterations Code :- module numdigits(a,b); parameter n=100; input [0:n-1] a;

问题 So I would like to simulate a simple register file and test it. But it's been pretty confusing. I put together what I hope is a functional register file based on the notes that my professor provided, but now I'm struggling to create the test bench for it. I guess the main thing is how it has two DATA's and ADDR's (he showed an example of a memory file which only has one of each). Anyway, for my test bench I simply want to write some numbers to the register like in a for loop and instantiate

问题 I have read through all similar posts, but none address the issue I'm having, namely that line 41 assign Y[b]=~Y[b]; causes error "Illegal left-hand side in continuous assignment." I haven't assigned any regs so I don't see what the issue is. If I replace b with an actual number (say, 3) it works fine. But I need b as a variable here. // Hamming code 1-bit error correction module HCG(I,e,O); input [4:1] I; // input BCD input [7:1] e; // noise simulation wire [7:1] X; // Hamming code wire [7:1

问题 my code is as follows: module command_FSM(sys_R_Wn,sys_ADSn,cState,sys_REF_REQ,sys_REF_ACK,sys_INIT_DONE,sys_CLK); input sys_R_Wn; input sys_CLK; input sys_ADSn; output [4:0] cState; inout sys_INIT_DONE; input sys_REF_REQ; output sys_REF_ACK; wire sys_R_Wn; wire sys_ADSn; reg [4:0] cState; wire sys_INIT_DONE; wire sys_REF_REQ; reg sys_REF_ACK; reg mjet; integer i; parameter c_idle=5'b10000; parameter c_AR=5'b10001; parameter c_tRFC=5'b10010; parameter c_rdata=5'b10011; parameter c_tDAL=5

问题 For e.g. initial begin generate for(genvar i; i < 4; i++) //Code endgenerate end //initial I'm getting error using QuestaSim with the concept. "Near generate: syntax error, unexpected generate " 回答1: No. generate blocks are evaluated during elaboration time . While initial , always and other procedural blocks start at zero simulation time , that is, run-time. Referring to Systemverilog IEEE 1800-2012 : Generate schemes are evaluated during elaboration of the design . Although generate schemes

问题 Im writing a multiplexor of 4 bits as input and 1 as output. I have tray several ways, using cases, if, etc. but I keep getting this error: WARNING:PhysDesignRules:367 - The signal <A<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:Par:288 - The signal A<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. And when I program in

问题 How can I fetch the dimensions of a vector port using the vpi PLI routines? For example, for the vector port declaration "output [2:1] out;", how can I get the left dimension as 2 and right dimension as 1? I tried using vpiRange property but it seems that vpiRange property is not supported for Ports. Thanks! Putting the code here for clarity. vpiHandle lowconn = vpi_handle(vpiLowConn, portH); int dim = 0; int ldim[10]; int rdim[10]; vpiHandle range_itr = vpi_iterate(vpiRange, lowconn );

问题 I want to write a module in RAM and then read from the same into another module. How can I do this? I think there must be a way to pass RAM modules by referencing to other modules. For example: In module A: // write in ram and pass to module B ram ram_ins(); ram_ins.wr_en = 1; ram_ins.addr = 1; ram_ins.data_in = 1234; B b_ins(ram_ins); // pass by reference the ram_ins to the module B In module B: // read from ram ram_ins.addr = 1; reg [7:0] a; assign a = ram_ins.data_out Register a in module

问题 Signal driver_a is reassigned in the always block back to 0, but why is the always block not activating and assign value to driver_b ? always @(driver_a) begin driver_b = driver_a; driver_a = 0; end initial begin driver_a = 0; driver_b = 0; #2 driver_a = 8'h8; #2 driver_a = 8'hf; end In the waveform, I expect that after driver_a assigns its value to driver_b, then in the next line when driver_a gets assigned to 0, I'd expect the always block to reactivate and assign value 0 back to driver_b.

问题 I'm trying to generate an array of latches that are placed adjacent to each other using a Generate statement. I've been trying to use the Xilinx constraint "RLOC" to do this, but I haven't been successful. The code below won't successfully implement, but should illustrate what I'm trying to obtain. The issue with the code below is that "i" in the constraint call isn't being converted into a string, which is what the call is looking for. Does anyone have experience doing this? I'm using a