verilog

问题 what is the difference between casex and casez in Verilog ? I have searched about it and find this sentence : casez treats all z values in the case alternatives or the case expression as don't cares. All bit positions with z can also represented by ? in that position. casex treats all x and z values in the case item or the case expression as don't cares. for example , what is the difference between first one and second one: 1- casez (instr) 7'b1zzzzzzz: // arithmetic 7'b01zzzzzz: // load-reg

问题 I create this code from this curcuit Image Here And this is Error image Image Here This curcuit is Quadruple Bus Transcievers with 3-state outputs Verilog Code module Q52QuadrupleBus3Stlate(GAB,GBA,A,B); inout [3:0] A,B; input GAB,GBA; reg winA,winB; assign B = (GAB==1&&GBA==0) ? winA : 4'hz; assign A = (GAB==0&&GBA==1) ? winB : 4'hz; always @ (GAB or GBA) begin winA <= A; winB <= B; end endmodule Test Bench `timescale 1ps / 1ps module Q52TestBench; reg GAB; reg GBA; // Bidirs wire [3:0] A;

问题 When I go to simulate my top-level module in Xilinx Vivado 2016.4, I receive the peculiar error: ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [<...>/header.vh] I am using the built-in Vivado Simulator with Verilog 2001 specified. My header.vh looks like the following: `ifndef _header_vh_ `define _header_vh_ function integer clog2; input integer value; begin value = value - 1; for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 1; end endfunction

问题 When I go to simulate my top-level module in Xilinx Vivado 2016.4, I receive the peculiar error: ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [<...>/header.vh] I am using the built-in Vivado Simulator with Verilog 2001 specified. My header.vh looks like the following: `ifndef _header_vh_ `define _header_vh_ function integer clog2; input integer value; begin value = value - 1; for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 1; end endfunction

问题 I'd like to generate a reset signal (active high) that will last for a short period of time. I achieved it by following code: always @(posedge clk or negedge rst_n or posedge data) begin if(~rst_n | data) data <= 1'b0; else if(ena) data <= 1'b1; else data <= data; end Which is synthesized to D flip-flop : My generated signal will be 1 only for time equal to propagation time through OR gate. Now I want to remove rst_n signal. But if I do that, I receive the following D flip-flop : In that case

问题 I am trying to create a module for carry select adder in verilog. Everything works fine except the following portion where it is causing compilation error. module csa(a,b,s,cout); input[15:0] a,b; output [15:0] s; output cout; wire zero_c1, zero_c2,zero_c3,zero_c4,zero_c5; wire one_c1, one_c2,one_c3,one_c4,one_c5; wire temp_c1,temp_c2,temp_c3,temp_c4,temp_c5; wire [15:0] s_zero, s_one; initial begin fork fa(s[0], temp_c1,a[0],b[0],0); fa_one(s_zero[1],s_one[1],zero_c1,one_c1,a[1],b[1]); fa

问题 -This code is written in verilog using Modelsim 10.2d.The errors below indicate there is some problem with {cout,l3} assignment. module alu(a,b,bin,cin,op,cout,res); input [31:0] a,b; input [1:0] op; input bin,cin; reg [31:0] l1,l2,l3; output cout; output [31:0] res; assign l1 = a & b; assign l2 = a | b; initial if(bin == 1'b0) assign {cout,l3} = a + b + cin; else assign {cout,l3} = a - b + cin; mux4to1(l1,l2,l3,op,res); endmodule Error- v(14): LHS in procedural continuous assignment may not

问题 I have the following clock gate in the design: module my_clkgate(clko, clki, ena); // Clock gating latch triggered on the rising clki edge input clki; input ena; output clko; parameter tdelay = 0; reg enabled; always @ (clki, ena) begin if (!clki) begin enabled = ena; end end assign #(tdelay) clko = enabled & clki; endmodule When synthesising with Yosys, the resulting netlist instantiates (for the reg enabled ) a \$_DLATCH_P_ cell which is not included in the standard cell lib file I am using

问题 I looked through internet and couldn't find a clear and concise answer to my question. I want to know what'll happen if I drive same strength signals onto the same wire, one of them being logic 1 and the other being logic 0? What do I do if I want a signal to "win", for lack of a better word, depending on the situation? 回答1: Based on your comment, it sounds like you want a three-state bus. The basic structure to drive a three-state bus is: assign bus = enable ? out : 1'bz; Each module driving

问题 I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work: reg [7:0] transitionTable [0:7]; assign transitionTable[0] = 10; neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas? (In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive