Why I can not input value to inout type?

问题

• I create this code from this curcuit Image Here
• And this is Error image Image Here
• This curcuit is Quadruple Bus Transcievers with 3-state outputs

Verilog Code

module Q52QuadrupleBus3Stlate(GAB,GBA,A,B);
    inout [3:0] A,B;
    input GAB,GBA;
    reg winA,winB;
    assign  B = (GAB==1&&GBA==0) ? winA : 4'hz;
    assign  A = (GAB==0&&GBA==1) ? winB : 4'hz;
    always @ (GAB or GBA)
    begin
        winA <= A;
        winB <= B;
    end
endmodule

Test Bench

`timescale 1ps / 1ps
module Q52TestBench;
    reg GAB;
    reg GBA;
    // Bidirs
    wire [3:0] A;
    wire [3:0] B;
    parameter step = 10000;
    Q52QuadrupleBus3Stlate uut (GAB,GBA,A,B);
    initial begin
            GAB = 0;
            GBA = 0;
            A = 0; B = 0;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #(step*10) $finish;
    end
endmodule

回答1:

In Verilog:

• a wire must be driven by the output (or inout) of an instantiated module or an assign statement

• a reg must be driven by an always or initial block.

The decision as to whether a signal is to be a reg or a wire is driven primarily by what kind of code is driving the signal. Your signals A and B are driven by both the output of an instantiated module (uut) and by an initial block. So, you have a dilemma. Fortunately, there is a simple solution to this, which is commonly used in Verilog.

To drive an inout from an initial or always block, you need some extra signals in addition to the wires connected to your module inout ports (A and B in your case). You need a reg to correspond with each:

reg  [3:0] Ain;
reg  [3:0] Bin;

and an enable signal to correspond with each:

reg        Aen;
reg        Ben;

Then you need to implement some tri-state drivers using assign statements:

assign A = Aen ? Ain : 'bz;
assign B = Ben ? Bin : 'bz;

You need to drive the regs from the initial block, not the wires:

        Ain = 0; Bin = 0;

and finally, you also need to drive the enable signals from the same initial block:

        Aen = 1; Ben = 1;

Here's the complete code:

`timescale 1ps / 1ps
module Q52TestBench;
    reg GAB;
    reg GBA;
    // Bidirs
    wire [3:0] A;
    wire [3:0] B;
    reg  [3:0] Ain;
    reg  [3:0] Bin;
    reg        Aen;
    reg        Ben;
    parameter step = 10000;
    Q52QuadrupleBus3Stlate uut (GAB,GBA,A,B);
    assign A = Aen ? Ain : 'bz;
    assign B = Ben ? Bin : 'bz;
    initial begin
            GAB = 0;
            GBA = 0;
            Ain = 0; Bin = 0;
            Aen = 1; Ben = 1;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #(step*10) $finish;
    end
endmodule

https://www.edaplayground.com/x/5biz

来源：https://stackoverflow.com/questions/39344169/why-i-can-not-input-value-to-inout-type