Verilog Module Warning | 易学教程

问题

Im writing a multiplexor of 4 bits as input and 1 as output. I have tray several ways, using cases, if, etc. but I keep getting this error:

WARNING:PhysDesignRules:367 - The signal <A<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:Par:288 - The signal A<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

And when I program in my circuit design card (Basys), everything works fine, but the switch that is assign to A[2], doesnt work, here are my modules:

module Multi_4_1(
    input [3:0] A,
    input [1:0] S,
    output Z
    );

     wire w1, w2;

     Multi_2_1 a(.A(A[0]), .B(A[1]), .SEL(S[0]), .F(w1));
    Multi_2_1 b(.A(A[2]), .B(A[3]), .SEL(S[1]), .F(w2));
     Multi_2_1 c(.A(w1), .B(w2), .SEL(S[1]), .F(Z));

endmodule

module Multi_2_1(
    input A,
    input B,
    input SEL,
    output F
    );

     assign F = (~SEL&A)|(SEL&B);

endmodule

And this is where I assign the terminals to the card, but this I have tried it with another projects and it works fine

NET "A[3]" LOC ="B4";   # sw3
NET "A[2]" LOC ="K3";
NET "A[1]" LOC ="L3";   # sw1
NET "A[0]" LOC ="P11";  # sw0, el de la derecha

NET "S[0]" LOC ="G3";   # sw4
NET "S[1]" LOC ="F3";   # sw5

NET "Z" LOC ="M5";   # L0, el de la derecha

回答1:

Your multiplexer has an incorrect design.

This is your truth table:

S=00 => Z=A[0]
S=01 => Z=A[1]
S=10 => Z=A[3]
S=11 => Z=A[3]

Thus A[2] can never be an output, so it is 'unloaded', and your synthesis tool is warning you of this. You probably intend for Mux b to use sel(S[0]).

来源：https://stackoverflow.com/questions/14823586/verilog-module-warning

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