Synthesizable array of XY values

问题

I want to create an array in Verilog which is going to contain the values x, y of a given function. So each content of the array is going to contain a value of x and a value of y. So lets say that I have the following values for (x,y)

(3,2)
(5,10)
(1,5)

The final array will look something like this:

Table[i][x][y]

Table[0][3][2]
Table[1][5][10]
Table[2][1][5]

Is it possible to make this array in Verilog and be synthesizable? If so, how can I access each point on this array?

回答1:

I think that what you want to get is an array in which an element can hold two numbers. They way you have presented it is weird. What you say with your example code is that you have a tri-dimensional array, in which some elements with certain values for i,x and y, will have a value, but you don't specify what value.

What you say in the text is that you want a table of i elements, in which each element will have two values: one for x and one for y. That is something that we can work out, but not with the implementation (the tri-dimensional array) you provide.

That said, you must first consider how is the nature of your x,y values you want to store in the table. Verilog work best with integers, so I will assume that. You also need to know how many bits your integers will use. Let's say they will use 8 bits, so valid x,y values are in the range [-128,+127] is sign is considered.

Now you must know how many x,y pairs you want to store in your table. Let's say it's N values, where N is some kind of parameter to your module.

Then, the table would be instantiated like this:

reg [15:0] Table[0..N-1];

So, Table[i][7:0] can hold one 8 bit value, for example, y, and Table[i][15:8] can hold another 8 bit value, say x.

To initialize this Table, in a synthesizable way, the most common method is to add a reset signal to your module and use it to initialize Table contents, like this:

reg [15:0] Table[0..N-1];
integer i;
always @(posedge clk) begin
  if (reset == 1'b1) begin
    Table[0] <= {8'd3, 8'd2};
    Table[1] <= {8'd5, 8'd10};
    Table[2] <= {8'd1, 8'd5};
    for (i=3;i<N;i=i+1)   // initialize the rest of Table to 0,0
      Table[i] <= {8'd0, 8'd0};
  end
  else ......
end

To access the point at location i, you simply use:

Table[i][15:8] for X value
Table[i][7:0] for Y value

If targetting a Xilinx device, you can also initialize contents of a register, be it in distributed RAM or block RAM, using an initial block

reg [15:0] Table[0..N-1];
integer i;
initial begin
  Table[0] = {8'd3, 8'd2};
  Table[1] = {8'd5, 8'd10};
  Table[2] = {8'd1, 8'd5};
  for (i=3;i<N;i=i+1)   // initialize the rest of Table to 0,0
    Table[i] = {8'd0, 8'd0};
end

来源：https://stackoverflow.com/questions/30030140/synthesizable-array-of-xy-values

标签

arrays

verilog