verilog

问题 What does data_mux mean here? Is it just a name for the block? if ((PORT_CONFIG == "32") && (P0 == 1'b1)) begin : data_mux ... end 回答1: These are block names. Especially useful with generate blocks. For example you can define a generate block such as genvar i; generate (for i = 0; i<10; i++) begin : structures reg my_reg; // ... .. other block descriptions // ... end endgenerate Then you can access the block elements later like structures[3].my_reg <= 1'b1; 回答2: Yes, it is just the name for

问题 What does data_mux mean here? Is it just a name for the block? if ((PORT_CONFIG == "32") && (P0 == 1'b1)) begin : data_mux ... end 回答1: These are block names. Especially useful with generate blocks. For example you can define a generate block such as genvar i; generate (for i = 0; i<10; i++) begin : structures reg my_reg; // ... .. other block descriptions // ... end endgenerate Then you can access the block elements later like structures[3].my_reg <= 1'b1; 回答2: Yes, it is just the name for

问题 I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would prefer an answer which is synthesizable. vhdl code: LIBRARY ieee; USE ieee.All; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; ENTITY adder_5 IS PORT ( a : IN integer ; b : IN integer; c : OUT integer ); END adder_5; ARCHITECTURE add

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 I am trying to create an Immediate Generator for RISC-V assembly but I have encountered with if statement. Here is my code in Verilog: module signextend(in, out, sel); parameter nin = 32; parameter nout = 32; input [nin-1:nin-25] in; input [2:0] sel; output [nout-1:0] out; if (sel == 3'b000) begin assign out[19:0] = in[31:12]; assign out[31:20] = {12{in[31]}}; end else if (sel == 3'b001) begin assign out[11:0] = in[31:20]; assign out[31:12] = {20{in[31]}}; end else if (sel == 3'b010) begin

问题 module hi ( input wire clk, output wire [6:0] a ); wire [7:0] b; assign b= 8'd24; assign a[6:0] = b[7:1]; initial $display ("%d", a); endmodule I get a high impedance 'z' output. Where am i going wrong? 回答1: You didn't give the assign statement a chance to propagate the values on the wires. The initial block executes first. Add a delay before the $display , or use $strobe instead. 来源： https://stackoverflow.com/questions/40035070/display-shows-unexpected-high-impedance-z-output

问题 module hi ( input wire clk, output wire [6:0] a ); wire [7:0] b; assign b= 8'd24; assign a[6:0] = b[7:1]; initial $display ("%d", a); endmodule I get a high impedance 'z' output. Where am i going wrong? 回答1: You didn't give the assign statement a chance to propagate the values on the wires. The initial block executes first. Add a delay before the $display , or use $strobe instead. 来源： https://stackoverflow.com/questions/40035070/display-shows-unexpected-high-impedance-z-output

问题 module hi ( input wire clk, output wire [6:0] a ); wire [7:0] b; assign b= 8'd24; assign a[6:0] = b[7:1]; initial $display ("%d", a); endmodule I get a high impedance 'z' output. Where am i going wrong? 回答1: You didn't give the assign statement a chance to propagate the values on the wires. The initial block executes first. Add a delay before the $display , or use $strobe instead. 来源： https://stackoverflow.com/questions/40035070/display-shows-unexpected-high-impedance-z-output