verilog

问题 I am new to Verilog, therefore I am facing some issues which I am not able to solve on my own. I have made a program that consists of 2 files, synthesis is successful but when I try to generate bitstream, then I face errors which are as follows. [Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[0]. [Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[10]. [Opt 31-37] Multi-driver net found in the design: uut/TX_Data_IBUF[11]. [Opt 31-37] Multi-driver net found

问题 Here is a short example code, which confused me. What is the rule to use values from the current or when from the previous simulation time-slot in verilog processes? module test(); reg clk, rst, r1, r2, r3; initial begin clk = 0; rst = 0; r1 = 0; r2 = 0; r3 = 0; @(posedge clk) rst = 1; end // initial always #5 begin : clkgen clk = ~clk; end /** TESTS **/ // PREVIOUS always @(posedge clk) begin : proc_non_block r1 = rst; end // CURRENT always @(posedge clk or posedge rst) begin : proc_async r2

问题 This question already has an answer here : Verilog: “… is not a constant” (1 answer) Closed 2 years ago . I have tried looking at different posts related to for loop inside an always block but my problem looks different. Here's the part of my code of interest : always@(posedge clk) begin for(i=2;i<UP_SPACES+2;i=i+1) begin //Ram_out if(up_addr_d2[3:0]==i) begin up_dout_t2 <= ram_out[(i+1)*32-1:i*32]; end end// for loop end I have declared i as an integer. Here the compiler gives the error 'i

问题 I want to define a macro during runtime in Verilog using environment variable. For example, I want to print some text to a file only when the DEBUG macro is defined as 1 . `define DEBUG 0 ... if(DEBUG) $fwrite(file,"Debug message"); How can I override the definition of DEBUG to 1 when running the simulation from command line or using environment variable? Alternatively, I could keep the macro undefined and use ifdef `ifdef(DEBUG) $fwrite(file,"Debug message"); In this case I would have to

问题 I have tried this multiple ways, I am a bit desperate now. I have tried to make this clock in my testbench the problem is in simulation it doesn't work or my simulation seems to freeze. I know it has to be the clock. initial begin forever begin clk = 0; #10 clk = ~clk; end end initial begin reset = 0; #15 L = 0; R = 0; H = 0; #20 L = 0; R = 0; H = 1; #25 L = 0; R = 1; H = 0; #30 L = 0; R = 1; H = 1; #35 L = 1; R = 0; H = 0; #45 L = 1; R = 0; H = 1; #50 L = 1; R = 1; H = 0; #55 L = 1; R = 1; H

问题 I'm using systemVerilog and I have a package that holds some of my modules parameter values (for example parameter SPI_RATE = 2_000_000; ). Is there any way I can set one value for simulation and a different one for synthesis? (I'm using ModelSim). For example I would like something like: if(IN_SIM) begin parameter SPI_RATE = 2_000_000; end else begin parameter SPI_RATE = 1_000_000; end Thanks! 回答1: Yes, that's possible. SystemVerilog supports conditional compiler directives such as `ifdef ,

问题 This was an interview question asked by a top 10 company of US. Code 1: always @(a or b or sel) begin if (sel == 1) c = a; else if (sel == 0) c =b; end This will create a mux. Code 2: Now "SEL" is removed from sensitivity. Will it still create mux? For the code below? If not, what logic will be created? always @(a or b) begin if (sel == 1) c = a; else if (sel == 0) c =b; end 回答1: Yes, this will still synthesize to a multiplexer 1 . A synthesis tool will interpret this RTL as if the

问题 This was an interview question asked by a top 10 company of US. Code 1: always @(a or b or sel) begin if (sel == 1) c = a; else if (sel == 0) c =b; end This will create a mux. Code 2: Now "SEL" is removed from sensitivity. Will it still create mux? For the code below? If not, what logic will be created? always @(a or b) begin if (sel == 1) c = a; else if (sel == 0) c =b; end 回答1: Yes, this will still synthesize to a multiplexer 1 . A synthesis tool will interpret this RTL as if the

问题 What does data_mux mean here? Is it just a name for the block? if ((PORT_CONFIG == "32") && (P0 == 1'b1)) begin : data_mux ... end 回答1: These are block names. Especially useful with generate blocks. For example you can define a generate block such as genvar i; generate (for i = 0; i<10; i++) begin : structures reg my_reg; // ... .. other block descriptions // ... end endgenerate Then you can access the block elements later like structures[3].my_reg <= 1'b1; 回答2: Yes, it is just the name for

问题 What does data_mux mean here? Is it just a name for the block? if ((PORT_CONFIG == "32") && (P0 == 1'b1)) begin : data_mux ... end 回答1: These are block names. Especially useful with generate blocks. For example you can define a generate block such as genvar i; generate (for i = 0; i<10; i++) begin : structures reg my_reg; // ... .. other block descriptions // ... end endgenerate Then you can access the block elements later like structures[3].my_reg <= 1'b1; 回答2: Yes, it is just the name for