For loop inside an always block with conditional statement giving unexpected error [duplicate]

问题

This question already has an answer here:

Verilog: “… is not a constant” (1 answer)

Closed 2 years ago.

I have tried looking at different posts related to for loop inside an always block but my problem looks different. Here's the part of my code of interest :

   always@(posedge clk) begin
     for(i=2;i<UP_SPACES+2;i=i+1) begin  //Ram_out
        if(up_addr_d2[3:0]==i) 
        begin
          up_dout_t2     <= ram_out[(i+1)*32-1:i*32];                                                                                                    
        end
     end// for loop
  end

I have declared i as an integer. Here the compiler gives the error 'i is not a constant'. I was not sure if one can code this way and was expecting a multidriver error but this error i dont understand. Please throw light.

回答1:

This line is illegal:

up_dout_t2     <= ram_out[(i+1)*32-1:i*32];

It is illegal to have a variable value of the right hand side of the colon in a part-select. Basically, this is illegal:

i[a+3 : a]

Instead, you have to say:

i[a+3 -: 4]

where a+3 is the starting index, -: means count down and 4 is the width. So, instead of

i[a : a+3] 

you have to say:

i[a +: 4]

The direction of the index of i doesn't matter. These lines of code would work for either

reg [big:little] i;

or

reg [little:big] i;

So, your line of code should be:

up_dout_t2     <= ram_out[(i+1)*32-1 -: 32];

or:

up_dout_t2     <= ram_out[i*32 +: 32];

来源：https://stackoverflow.com/questions/52186389/for-loop-inside-an-always-block-with-conditional-statement-giving-unexpected-err