When does verilog use values from the current and when from the previous timeslot?

问题

Here is a short example code, which confused me. What is the rule to use values from the current or when from the previous simulation time-slot in verilog processes?

module test();

    reg clk, rst, r1, r2, r3;

    initial begin
        clk = 0;
        rst = 0;
        r1 = 0;
        r2 = 0;
        r3 = 0;

        @(posedge clk)
        rst = 1;
    end // initial

    always #5 begin : clkgen
        clk = ~clk;
    end


    /** TESTS **/

    // PREVIOUS
    always @(posedge clk) begin : proc_non_block
        r1 = rst;
    end

    // CURRENT
    always @(posedge clk or posedge rst) begin : proc_async
        r2 <= rst;
    end

    // PREVIOUS
    always @(posedge clk or negedge rst) begin : proc_async_neg
        r3 <= rst;
    end

endmodule // test

Here is the result of the simulation. (Questasim 10.4C)

Experiments above shows me that the current value of a given signal is used only if the given signal has an active event at the current simulation time-slot. Am I right? Any details?

回答1:

Verilog always uses the current value of variable. This issue is when the current value gets updated when making an assignment. Since you wrote to rst with a blocking assignment in a process that unblocks on the posedge of clk, there is a race condition with other blocks that also unblock on the posedge of clk. There is no defined ordering of when each always process unblocks relative to when the Initial process unblocks making its assignment to rst . So it appears as you get the _old_ value ofrst ` because the assignment has not happened yet.

The general rule is: use non-blocking assignments to a variable whenever one process writes, and another process reads the same variable and all the process are synchronized to the same clock event.

来源：https://stackoverflow.com/questions/50859205/when-does-verilog-use-values-from-the-current-and-when-from-the-previous-timeslo

标签

verilog

simulation