verilog

问题 I can't seem to be able to create a vim macro that does the following: Source: this_is_a_bus[10:0] another_bus[2:0] Required Dest: this_is_a_bus[10] this_is_a_bus[9] this_is_a_bus[8] this_is_a_bus[7] this_is_a_bus[6] this_is_a_bus[5] this_is_a_bus[4] this_is_a_bus[3] this_is_a_bus[2] this_is_a_bus[1] this_is_a_bus[0] another_bus[2] another_bus[1] another_bus[0] What I tried to do: I can search for \d\+:\d\+ and put the cursor on the first number, then copy that with yw to the memory. However

问题 When writing a Verilog test bench to verify a module is there any way to access a particular variable local to that module from the test bench? 回答1: Use hierarchical reference to access cross-hierarchical variable. For accessing variable in the sub-hierarchy of current module, you can use relative path, as in example below, "dut.localvar". For accessing variable of a module which is not part of current module hierarchy, use absolute path from the top, e.g., "testbench.dut.localvar". module

问题 I know how to design a 4x4 array multiplier , but if I follow the same logic , the coding becomes tedious. 4 x 4 - 16 partial products 64 x 64 - 4096 partial products. Along with 8 full adders and 4 half adders, How many full adders and half adders do I need for 64 x 64 bit. How do I reduce the number of Partial products? Is there any simple way to solve this ? 回答1: Whenever tediously coding a repetitive pattern you should use a generate statement instead: module array_multiplier(a, b, y);

问题 I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got so far: [EDIT: Changed the selection statement slightly] `timescale 1ns / 1ps module SignExtender( CLK, extend, extended ); input[7:0] extend; input CLK; output[15:0] extended; reg[15:0] extended; wire[7:0] extend; always begin while (CLK == 1) extended[7:0] = extend[7:0]; extended[15:8] = {8{extend[7]}}; end endmodule I added the while (CLK == 1) thinking that would

问题 I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got so far: [EDIT: Changed the selection statement slightly] `timescale 1ns / 1ps module SignExtender( CLK, extend, extended ); input[7:0] extend; input CLK; output[15:0] extended; reg[15:0] extended; wire[7:0] extend; always begin while (CLK == 1) extended[7:0] = extend[7:0]; extended[15:8] = {8{extend[7]}}; end endmodule I added the while (CLK == 1) thinking that would

问题 input [31:0] write_data; input [4:0] write_reg; reg [31:0] registers [31:0]; always @(*) assign registers[write_reg] = write_data; I have a 32-bit input write_data , which i want to an assign corresponding index which i get from write reg.Error says you cant do continuous assignment which i think causes by always@(*) but if i remove that It says object "registers" on left-hand side of assignment must have a net type and its another error. 回答1: assign inside an always block is the procedural

问题 I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code: output reg[3:0]x; // line 149 output wire error; output wire overflow; always @* begin if(error || overflow) begin assign x = 4'b1111; // line 155 assign error = ~error; assign overflow = ~overflow; end else begin assign x = opcode; end end I get following error messages: uut is my instantiation unit in my testbench called main 回答1: The code in the example has several issues.

问题 I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code: output reg[3:0]x; // line 149 output wire error; output wire overflow; always @* begin if(error || overflow) begin assign x = 4'b1111; // line 155 assign error = ~error; assign overflow = ~overflow; end else begin assign x = opcode; end end I get following error messages: uut is my instantiation unit in my testbench called main 回答1: The code in the example has several issues.

问题 the code doesn't Works. I am getting "Malformed statement" error. Can you guys help me? it appears in ring_c1 module instantiation. Thanks in advance. module log2(N,clk); `include "parameters.vh" input [7:0] N; reg [7:0] aux ; reg [7:0] last_log; reg [7:0] div_last; output reg [7:0] y; // assign aux = N; input clk; parameter high = 1; always @ (posedge clk) begin ring_c1 ri1 ( aux[0], div_last); aux = aux >> 1; if (aux < 1 ) begin ring_c1 r1v ( high, div_last); log_Finale (last_log, div_last)

问题 `timescale 1ps/1ps module test1(output t1, input t2, input t3); always begin #1 or U_t1(t1, t2, t3); end endmodule I wanted this to "or" t2 and t3 and store it in t1 with a 1ps delay, but I am getting a "malformed statement" error. 回答1: Refer to IEEE Std 1800-2012, section 28. Gate-level and switch-level modeling for the proper syntax of instantiating a gate with a delay. An always block should not be used this way. The following will add a 1ps delay on the output: `timescale 1ps/1ps module