malformed statement in verilog3

问题

the code doesn't Works. I am getting "Malformed statement" error. Can you guys help me? it appears in ring_c1 module instantiation. Thanks in advance.

module log2(N,clk);

`include "parameters.vh"

input [7:0] N;
reg [7:0] aux ;
reg [7:0] last_log;
reg [7:0] div_last;
output reg [7:0] y;
// assign aux = N;
input clk;

parameter high = 1;

always @ (posedge clk) 
begin 
    ring_c1 ri1 ( aux[0], div_last);
    aux = aux >> 1;

    if (aux < 1 )  
        begin   
            ring_c1 r1v ( high, div_last);
            log_Finale (last_log, div_last);

            y = y + last_log;

       end      
    else
        y = y+1;
    end 
endmodule 

回答1:

You can't instance components in an always statement.

You have to place them outside the always and then use them.

回答2:

To expand on @Oldfart's comment: You are trying to write RTL (register transfer language) as if it was a programming language expect with module instantiation instead of function calls--it isn't. You are using code to describe real hardware, gates, flip-flops, banks of memory, etc. If you can't envision the hardware that your code will produce, you're doing it wrong. You can't have hardware appear and disappear in real time based on signals in your design. However, you can have the modules instantiated and use multiplexer logic to design which module outputs you wish to use.

来源：https://stackoverflow.com/questions/51758343/malformed-statement-in-verilog3