Why is this a malformed statement?

问题

`timescale 1ps/1ps
module test1(output t1, input t2, input t3);
   always begin
        #1 or U_t1(t1, t2, t3);
   end
endmodule

I wanted this to "or" t2 and t3 and store it in t1 with a 1ps delay, but I am getting a "malformed statement" error.

回答1:

Refer to IEEE Std 1800-2012, section 28. Gate-level and switch-level modeling for the proper syntax of instantiating a gate with a delay. An always block should not be used this way. The following will add a 1ps delay on the output:

`timescale 1ps/1ps
module test1(output t1, input t2, input t3);
    or #1 U_t1 (t1, t2, t3);
endmodule

来源：https://stackoverflow.com/questions/42564267/why-is-this-a-malformed-statement