问题
What does data_mux
mean here? Is it just a name for the block?
if ((PORT_CONFIG == "32") && (P0 == 1'b1))
begin : data_mux
...
end
回答1:
These are block names. Especially useful with generate blocks. For example you can define a generate block such as
genvar i;
generate (for i = 0; i<10; i++)
begin : structures
reg my_reg;
// ...
.. other block descriptions
// ...
end
endgenerate
Then you can access the block elements later like
structures[3].my_reg <= 1'b1;
回答2:
Yes, it is just the name for the begin
/end
block. Refer to the free IEEE Std 1800-2012 (section 9.3.4 Block names). In most cases the block label is optional.
来源:https://stackoverflow.com/questions/41990552/verilog-what-does-begin-followed-by-colon-and-a-variable-mean