pci-e

I am working on a DMA routine to transfer data from PC to a FPGA on a PCIe card. I read DMA-API.txt and LDD3 ch. 15 for details. However, I could not figure out how to do a DMA transfer from PC to a consistent block of iomem on the PCIe card. The dad sample for PCI in LDD3 maps a buffer and then tells the card to do the DMA transfer, but I need the PC to do this. What I already found out: Request bus master pci_set_master(pdev); Set the DMA mask if (dma_set_mask(&(pdev->dev), DMA_BIT_MASK(32))) { dev_err(&pdev->dev,"No suitable DMA available.\n"); goto cleanup; } Request a DMA channel if

If I have only the physical address of the memory buffer to which is mapped the device buffer via the PCI-Express BAR (Base Address Register), how can I map this buffer to user-space ? For example, how does usually the code should look like in Linux-kernel? unsigned long long phys_addr = ...; // get device phys addr unsigned long long size_buff = ...l // get device size buff // ... mmap(), remap_pfn_range(), Or what should I do now? On: Linux x86_64 From: https://stackoverflow.com/a/17278263/1558037 ioremap() maps a physical address into a kernel virtual address. remap_pfn_range() maps

On my CUDA program I see large variability between different runs (upto 50%) in communication time which include host to device and device to host data transfer times over PCI Express for pinned memory. How can I explain this variability? Does it happen when the PCI controller and memory controller is busy performing other PCIe transfers? Any insight/reference is greatly appreciated. The GPU is Tesla K20c, the host is AMD Opteron 6168 with 12 cores running the Linux operating system. The PCI Express version is 2.0. talonmies The system you are doing this on is a NUMA system, which means that

After going through some basics documents what I understood is, Base Address Register is Address space which can be accessed by PCIe IP. PCIe IP can either transmit data in Base Address Register or it can write received data on to it. Am I right? Or missing anything? Paebbels I think this is a very basic question and I would suggest to read: PCI Express Base 3.1 Specification (pcisig.com) or PCI Express Technology 3.0 (MindShare Press) book A Base Address Register (BAR) is used to: - specify how much memory a device wants to be mapped into main memory, and - after device enumeration, it holds

If I transfer a single byte from a CUDA kernel to PCI-E to the host (zero-copy memory), how much is it slow compared to transferring something like 200 Megabytes? What I would like to know, since I know that transferring over PCI-E is slow for a CUDA kernel, is: does it change anything if I transfer just a single byte or a huge amount of data? Or perhaps since memory transfers are performed in "bulks", transferring a single byte is extremely expensive and useless with respect to transferring 200 MBs? Hope this pic explain everything. The data is generated by bandwidthTest in CUDA samples. The