gnu-make

GNU Make 3.82 gcc 4.7.2 c89 I have the following make file: INC_PATH=-I/home/dev_tools/apr/include/apr-1 LIB_PATH=-L/home/dev_tools/apr/lib LIBS=-lapr-1 -laprutil-1 RUNTIME_PATH=-Wl,-rpath,/home/dev_tools/apr/lib CC=gcc CFLAGS=-Wall -Wextra -g -m32 -O2 -D_DEBUG -D_THREAD_SAFE -D_REENTRANT -D_LARGEFILE64_SOURCE $(INC_PATH) SOURCES=$(wildcard src/*.c) OBJECTS=$(patsubst %.c, %.o, $(SOURCES)) EXECUTABLE=bin/to all: build $(EXECUTABLE) $(EXECUTABLE): $(OBJECTS) $(CC) $(CFLAGS) -o $@ $(RUNTIME_PATH) $(OBJECTS) $(LIB_PATH) $(LIBS) $(OBJECTS): $(SOURCES) $(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $

In the GNU Makefile manual, it mentions these prefixes. If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’). What do these prefixes do, and where are they mentioned? They control the behaviour of make for the tagged command lines: @ suppresses the normal 'echo' of the command that is executed. - means ignore the exit status of the command that is executed (normally, a non-zero exit status would stop that part of the build). + means 'execute this command under make -n ' (or 'make -t' or 'make -q') when commands

In my GNUmakefile, I would like to have a rule that uses a temporary directory. For example: out.tar: TMP := $(shell mktemp -d) echo hi $(TMP)/hi.txt tar -C $(TMP) cf $@ . rm -rf $(TMP) As written, the above rule creates the temporary directory at the time that the rule is parsed . This means that, even I don't make out.tar all the time, many temporary directories get created. I would like to avoid my /tmp being littered with unused temporary directories. Is there a way to cause the variable to only be defined when the rule is fired, as opposed to whenever it is defined? My main thought is to

I'm trying to do this in a makefile and it fails horribly: M_ARCH := $(shell g++ -dumpmachine | awk '{split($1,a,"-");print a[1]}') do you know why? I guess it has to do with escaping, but what and where? It's the dollar sign, in makefiles you'll have to type $$ to get a single dollar sign: M_ARCH := $(shell g++ -dumpmachine | awk '{split($$1,a,"-");print a[1]}') Make is quite lispy when you get down to it. Here's a non-awk version that does the same thing: space := $() # M_ARCH := $(firstword $(subst -,$(space),$(shell g++ -dumpmachine))) all: $(info $(M_ARCH)) 来源： https://stackoverflow.com

It's been a while since I've used make , so bear with me... I've got a directory, flac , containing .FLAC files. I've got a corresponding directory, mp3 containing MP3 files. If a FLAC file is newer than the corresponding MP3 file (or the corresponding MP3 file doesn't exist), then I want to run a bunch of commands to convert the FLAC file to an MP3 file, and copy the tags across. The kicker: I need to search the flac directory recursively, and create corresponding subdirectories in the mp3 directory. The directories and files can have spaces in the names, and are named in UTF-8. And I want to

I'm having trouble with trying to use make to place object files in a separate subdirectory, probably a very basic technique. I have tried to use the information in this page: http://www.gnu.org/software/hello/manual/make/Prerequisite-Types.html#Prerequisite-Types I get the following output from make: make: *** No rule to make target `ku.h', needed by `obj/kumain.o'. Stop. However ku.h is a dependency not a target (although it's obviously #included within the c source files). When I don't try to use a subdirectory for object files (i.e. miss out the OBJDIR parts) it works fine. Why does make