gnu-make | 易学教程

How to get the second dependency file using Automatic Variables in a Makefile?

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问题 I need to get the nth dependency file from a rule, something similar to $n in bash. I need this because I'd like to feed in individual dependency files as options to the build program. Here's an example: dep.o: dep.src config1.cfg config2.cfg parse -cfg1 $2 -cfg2 $3 -o $@ $< Is it possible? 回答1: dep.o: dep.src config1.cfg config2.cfg @echo the second preq is $(word 2,$^), the third is $(word 3,$^) 来源： https://stackoverflow.com/questions/11424204/how-to-get-the-second-dependency-file-using

Building C-program “out of source tree” with GNU make

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I would like to build a C-project for my microcontroller with the GNU make tool. I would like to do it in a clean way, such that my source code is not cluttered with object files and other stuff after the build. So imagine that I have a project folder, called "myProject" with two folders in it: - myProject | |---+ source | '---+ build The build folder only contains a makefile. The figure below shows what should happen when I run the GNU make tool: So GNU make should create an object file for each .c source file it can find in the source folder. The object files should be structured in a

Making CMake print commands before executing

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问题 I'm working on a large C++ project built with CMake on Linux. CMake runs okay, producing a horde of Makefiles in the tree of modules and applications. Running GNU make leads to linker errors. How can I get make to print out the exact commands before running them? The -d option does not print the commands, but plenty of information that hasn't been helpful. The -n option prints all the commands, but does not run them, so I can't tell were exactly the trouble is. Examining the stdout from make

How to install and use “make” in Windows?

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问题 I'm following the instructions of someone whose repository I cloned to my machine. What I want is simple: to be able to use the make command as part of setting up the code environment. But I'm using Windows, and I searched online only to find a make.exe file to download, a make-4.1.tar.gz file to download (I don't know what to do with it next), and things about downloading MinGW (for GNU; but after installing it I didn't find any mention of "make"). I don't want a GNU compiler or related

Difference between CPPFLAGS and CXXFLAGS in GNU Make

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What's the difference between CPPFLAGS and CXXFLAGS in GNU Make? Kieron CPPFLAGS is supposed to be for flags for the C P re P rocessor; CXXFLAGS is for flags for the C++ compiler. The default rules in make (on my machine, at any rate) pass CPPFLAGS to just about everything, CFLAGS is only passed when compiling and linking C, and CXXFLAGS is only passed when compiling and linking C++. Christoph By default, CPPFLAGS will be given to the C preprocessor, while CXXFLAGS will be given to the C++ compiler. The GNU Make Manual is a good resource for questions like this (see Implicit Variables ).

Escaping colons in filenames in a Makefile

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问题 Is there a way to get GNU make to work correctly with filenames that contain colons? The specific problem I'm running into happens to involve a pattern rule. Here's a simplified version that does not depend on cutting and pasting tab characters: % make --version GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. This program built

How to add custom targets in a qmake generated Makefile?

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问题 Today when I play with Qt I use qmake to generate the Makefile, and that works quite well. However sometimes I want to add more stuff to the generated Makefile, without having to edit the generated Makefile. Let's say that we beside the source code have a Doxygen directory, and there I need to run some doxygen commands to generate the documentation. So it would be nice to have this as a target in the main Makefile. But as default qmake do not understand this type of extra stuff. So can I add

Disable make builtin rules and variables from inside the make file

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问题 I want to disable builtin rules and variables as per passing the -r and -R options to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome. I've found several references to using MAKEFLAGS, and had similar problems. 回答1: You could start the Makefile with a #! and call it something different so people don't try to use make directly: #!/usr/bin/make -rRf # ... This will cause horrific problems if GNU make is not the system

Makefile rule that depends on all files under a directory (including within subdirectories)

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问题 One rule in my Makefile zips an entire directory ( res/ ) into a ZIP file. Obviously, this rule needs to execute when any file under the res/ directory changes. Thus, I want the rule to have as a prerequisite all files underneath that directory. How can I implement this rule? In Bash with the globstar option enabled, you can obtain a list of all the files in that directory using the wildcard pattern res/**/* . However, it doesn't seem to work if you specify it as a prerequisite in the

How to change the extension of each file in a list with multiple extensions in GNU make?

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问题 In a GNU makefile, I am wondering if it is possible, with an file list input, to make a file list output with new extensions. In input, I get this list: FILES_IN=file1.doc file2.xls And I would like to build this variable in my makefile from FILES_IN variable: FILES_OUT=file1.docx file2.xlsx Is it possible ? How ? It's quite difficult because I have to parse file list, and detect each extension (.doc, .xls) to replace it to correct extension. 回答1: Substituting extensions in a list of