gnu-make

List goals/targets in GNU make that contain variables in their definition

由 时光怂恿深爱的人放手 提交于 2019-11-27 09:00:10
问题 I have a fairly large makefile that creates a number of targets on the fly by computing names from variables. (eg foo$(VAR) : $(PREREQS)). Is there any way that gnu make can be convinced to spit out a list of targets after it has expanded these variables? I'd like to be able to get the targets for an aribitrary makefile. I'm trying to write a completion function for my shell. 回答1: Can you parse the output from make -pn (i.e. make --print-data-base --dry-run )? It prints out all the variables,

Included Makefile's parent directory

由 折月煮酒 提交于 2019-11-27 08:40:11
问题 I want to describe each submake's dependencies in a file that a top-level Makefile can include. This is to allows for a recursive make setup (with all of the power of instanced variables and relative pathing) but with all dependencies described in a top-level make to increase compile speed and parallelism. For instance, let's assume we have a directory tree that looks like this: project/ |-- lib1 | |-- Makefile | `-- Makefile.reg |-- lib2 | |-- Makefile | `-- Makefile.reg |-- Makefile `--

Wildcard targets in a Makefile

由 为君一笑 提交于 2019-11-27 08:11:13
How can I compact the folllowing Makefile targets? $(GRAPHDIR)/Complex.png: $(GRAPHDIR)/Complex.dot dot $(GRAPHDIR)/Complex.dot -Tpng -o $(GRAPHDIR)/Complex.png $(GRAPHDIR)/Simple.png: $(GRAPHDIR)/Simple.dot dot $(GRAPHDIR)/Simple.dot -Tpng -o $(GRAPHDIR)/Simple.png $(GRAPHDIR)/IFileReader.png: $(GRAPHDIR)/IFileReader.dot dot $(GRAPHDIR)/IFileReader.dot -Tpng -o $(GRAPHDIR)/IFileReader.png $(GRAPHDIR)/McCabe-linear.png: $(GRAPHDIR)/McCabe-linear.dot dot $(GRAPHDIR)/McCabe-linear.dot -Tpng -o $(GRAPHDIR)/McCabe-linear.png graphs: $(GRAPHDIR)/Complex.png $(GRAPHDIR)/Simple.png $(GRAPHDIR)

make: Using target specific variables in prerequisites

由 大城市里の小女人 提交于 2019-11-27 05:52:51
问题 I'm trying to write a Makefile where prerequisites using target specific variables version= target1: override version=1 target1: package target2: override version=2 target2: package package: dir=package-${version}\ package: source source: src/${version}.c When i run make the version variable is in target package and source empty. What I'm doing wrong? 回答1: Use Secondary Expansion: .SECONDEXPANSION: package: dir=package-$${version} package: source source: src/$${version}.c UPD. This answer is

How do I write the 'cd' command in a makefile?

由 狂风中的少年 提交于 2019-11-27 05:46:51
For example, I have something like this in my makefile: all: cd some_directory But when I typed make I saw only 'cd some_directory', like in the echo command. It is actually executing the command, changing the directory to some_directory , however, this is performed in a sub-process shell, and affects neither make nor the shell you're working from. If you're looking to perform more tasks within some_directory , you need to add a semi-colon and append the other commands as well. Note that you cannot use newlines as they are interpreted by make as the end of the rule, so any newlines you use for

Compile all C files in a directory into separate programs

由 空扰寡人 提交于 2019-11-27 05:25:00
问题 Is there a way using GNU Make of compiling all of the C files in a directory into separate programs, with each program named as the source file without the .c extension? 回答1: SRCS = $(wildcard *.c) PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) %: %.c $(CC) $(CFLAGS) -o $@ $< 回答2: I don't think you even need a makefile - the default implicit make rules should do it: $ ls src0.c src1.c src2.c src3.c $ make `basename -s .c *` cc src0.c -o src0 cc src1.c -o src1 cc src2.c -o src2 cc src3.c -o

GNU make: should the number of jobs equal the number of CPU cores in a system?

由 蓝咒 提交于 2019-11-27 05:03:18
问题 There seems to be some controversy on whether the number of jobs in GNU make is supposed to be equal to the number of cores, or if you can optimize the build time by adding one extra job that can be queued up while the others "work". Is it better to use -j4 or -j5 on a quad core system? Have you seen (or done) any benchmarking that supports one or the other? 回答1: I would say the best thing to do is benchmark it yourself on your particular environment and workload. Seems like there are too

Suppress make rule error output

由 无人久伴 提交于 2019-11-27 04:41:29
问题 I have an rule that creates a directory bin: -mkdir $@ However after the first time the directory has been generated, I receive this output: mkdir bin mkdir: cannot create directory `bin': File exists make: [bin] Error 1 (ignored) Is there some way I can only run the rule if the directory doesn't exist, or suppress the output when the directory already exists? 回答1: The traditional way to handle directory creation is to use a stamp file that is depended on and creates the dir as a side effect.

Makefile ifeq logical AND

由 冷暖自知 提交于 2019-11-27 02:03:53
问题 I would like to check multiple conditions in an if loop of GNU make file. Here's an example: ifeq ($(TEST_FLAG),TRUE && ($(DEBUG_FLAG),FALSE)) true statement else false statement endif What's the right way to do it? 回答1: You can use ifeq with a concatenation of your values, eg. ifeq ($(TEST_FLAG)$(DEBUG_FLAG),TRUEFALSE) do something endif It's also possible to use the Conditional functions, which are more likely to be useful in a loop (as ifeq will probably not do what you expect in a loop,

How to speed up Compile Time of my CMake enabled C++ Project?

由 筅森魡賤 提交于 2019-11-27 01:52:41
I came across several SO questions regarding specific aspects of improving the turn-around time of CMake enabled C++ projects lately (like "At what level should I distribute my build process?" or "cmake rebuild_cache for just a subdirectory?" ), I was wondering if there is a more general guidance utilizing the specific possibilities CMake offers. If there is probably no cross-platform compile time optimization, I'm mainly interested in Visual Studio or GNU toochain based approaches. And I'm already aware of and investing into the generally recommended areas to speed up C++ builds: Change
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