gnu-make | 易学教程

Measure (profile) time spent in each target of a Makefile

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问题 Is there a way to echo the (system, user, real) time spent in each target of a Makefile recursively when I do make all ? I'd like to benchmark the compilation of a project in a more granular way than just time make all . Ideally, it would echo a tree of the executed target, each one with the time spent in all its dependencies. It'd be great also if it could work with -j (parallel make). And by the way my Makefile is non-recursive (doesn't spawn another make instance for each main targets).

How to trace Makefile targets for troubleshooting?

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问题 We have a long and complicated Makefile in our build system. Is there a good way to trace exactly which targets get executed for a given make invocation? 回答1: Use make -d or make --debug[=flags] options: ‘-d’ Print debugging information in addition to normal processing. The debugging information says which files are being considered for remaking, which file-times are being compared and with what results, which files actually need to be remade, which implicit rules are considered and which are

Makefile to put object files from source files different directories into a single, separate directory?

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I'm using UnitTest++ to allow me to create unit tests for some C++ code (that should build on Linux or Mac OS X). I have a directory structure like this: src - Foo.cpp - Bar.cpp test - FooTest.cpp - BarTest.cpp - Main.cpp - Makefile UnitTest++ - libUnitTest++.a And this Makefile (adapted from the UnitTest++ Makefile) works nicely (with GNU make): test = TestFooAndBar src = ../src/Foo.cpp \ ../src/Bar.cpp test_src = Main.cpp \ FooTest.cpp \ BarTest.cpp lib = ../UnitTest++/libUnitTest++.a objects = $(patsubst %.cpp,%.o,$(src)) test_objects = $(patsubst %.cpp,%.o,$(test_src)) .PHONY: all all: $

How to manually call another target from a make target?

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问题 I would like to have a makefile like this: cudaLib : # Create shared library with nvcc ocelotLib : # Create shared library for gpuocelot build-cuda : cudaLib make build build-ocelot : ocelotLib make build build : # build and link with the shared library I.e. the *Lib tasks create a library that runs cuda directly on the device, or on gpuocelot respectively. For both build tasks I need to run the same build steps, only creating the library differs. Is there an alternative to running make

What does @: (at symbol colon) mean in a Makefile?

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What does the following do in a Makefile? rule: $(deps) @: I can't seem to find this in the make manual. It means "don't echo this command on the output." So this rule is saying "execute the shell command : and don't echo the output. Of course the shell command : is a no-op, so this is saying "do nothing, and don't tell." Why? The trick here is that you've got an obscure combination of two different syntaxes. The make(1) syntax is the use of an action starting with @, which is simply not to echo the command. So a rule like always: @echo this always happens won't emit echo this always happens

Append to GNU make variables via command line

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问题 I am using a GNU-make Makefile to build a C project with several targets ( all , clean , and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag). In the past, I have done that as follows (using the debugging symbols example): make target CFLAGS+=-g Unfortunately, this is not appending to the CFLAGS variable, but instead, clearing it and

Check if a program exists from a Makefile

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问题 How can I check if a program is callable from a Makefile? (That is, the program should exist in the path or otherwise be callable.) It could be used to check for which compiler is installed, for instance. E.g. something like this question, but without assuming the underlying shell is POSIX compatible. 回答1: Sometimes you need a Makefile to be able to run on different target OS's and you want the build to fail early if a required executable is not in PATH rather than to run for a possibly long

Run make in each subdirectory

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问题 I have a directory ( root_dir ), that contains a number of sub-directories ( subdir1, subdir2, ... ). I want to run the make in each directory in root_dir , using a Makefile placed in it. (Obviously supposed that each of subdir... has inside its own Makefile). So there are essentially two questions: How to get a list of directories in Makefile (automatically)? How to run make for each of the directories inside a make file? As I knwow in order to run make in a specific directory I heed to do

Why .SECONDARY does not work with patterns (%) while .PRECIOUS does?

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My question is to understand better what i missed in make process and .SECONDARY purpose vs .PRECIOUS, not to get my script working, since it does work already. I am using make to either open a emacs editor on a file ( java but irrelevant for purpose of this question ) or to create it with a template if not existing. If it works well with existing files, when using generated file it is removed at the end . I added prerequisite in .SECONDARY but didn't help, i had to add it in .PRECIOUS. This is question why wasn't it working in .SECONDARY ? . From what i found on SO .SECONDARY does not work

How to print out a variable in makefile

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问题 In my makefile, I have a variable 'NDK_PROJECT_PATH', my question is how can I print it out when it compiles? I read Make file echo displaying "$PATH" string and I tried: @echo $(NDK_PROJECT_PATH) @echo $(value NDK_PROJECT_PATH) Both gives me "build-local.mk:102: *** missing separator. Stop." Any one knows why it is not working for me? 回答1: You can print out variables as the makefile is read (assuming GNU make as you have tagged this question appropriately) using this method (with a variable