gnu-make

So I followed the Advanced Auto-Dependency Generation paper -- Makefile : SRCS := main.c foo.c main: main.o foo.o %.o: %.c $(CC) -MMD -MG -MT '$@ $*.d' -c $< -o $@ cp $*.d $*.tmp sed -e 's;#.*;;' -e 's;^[^:]*: *;;' -e 's; *\\$$;;' \ -e '/^$$/d' -e 's;$$; :;' < $*.tmp >> $*.d rm $*.tmp clean:: -rm *.o *.d main -include $(SRCS:.c=.d) main.c : #include "foo.h" int main(int argc, char** argv) { foo() ; return 0 ; } foo.h : #ifndef __FOO_H__ #define __FOO_H__ void foo() ; #endif -- and it works like a charm. But when foo.h becomes a generated file -- Makefile: ... HDRS := foo.h $(HDRS): mk_header

I'm trying to create a Makefile which places my .o files in a different directory than my source files. I'm trying to use a pattern rule so I don't have to create identical rules for each source & object file. My project structure looks something like: project/ + Makefile + src/ + main.cpp + video.cpp + Debug/ + src/ [contents built via Makefile:] + main.o + video.o My Makefile looks something like: OBJDIR_DEBUG = Debug OBJ_DEBUG = $(OBJDIR_DEBUG)/src/main.o $(OBJDIR_DEBUG)/src/video.o all: $(OBJ_DEBUG) $(OBJ_DEBUG): %.o: %.cpp $(CXX) $(CFLAGS_DEBUG) $(INC_DEBUG) -c $< -o $@ This doesn't work,

I want to disable builtin rules and variables as per passing the -r and -R options to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome. I've found several references to using MAKEFLAGS , and had similar problems. Disabling the built-in rules is done by writing an empty rule for .SUFFIXES : .SUFFIXES: Having erased the built-in rules, I'm not sure that erasing the built-in variables helps you much more than just remembering to set them yourself or not use them, but you could use something like $(foreach V $(shell make -p

One rule in my Makefile zips an entire directory ( res/ ) into a ZIP file. Obviously, this rule needs to execute when any file under the res/ directory changes. Thus, I want the rule to have as a prerequisite all files underneath that directory. How can I implement this rule? In Bash with the globstar option enabled , you can obtain a list of all the files in that directory using the wildcard pattern res/**/* . However, it doesn't seem to work if you specify it as a prerequisite in the Makefile: filename.jar: res/**/* Even after touch ing a file in res/ , Make still reports make: `filename.jar

In a GNU makefile, I am wondering if it is possible, with an file list input, to make a file list output with new extensions. In input, I get this list: FILES_IN=file1.doc file2.xls And I would like to build this variable in my makefile from FILES_IN variable: FILES_OUT=file1.docx file2.xlsx Is it possible ? How ? It's quite difficult because I have to parse file list, and detect each extension (.doc, .xls) to replace it to correct extension. Substituting extensions in a list of whitespace-separated file names is a common requirement, and there are built-in features for this. If you want to

I have a several Makefiles in app specific directories like this: /project1/apps/app_typeA/Makefile /project1/apps/app_typeB/Makefile /project1/apps/app_typeC/Makefile Each Makefile includes a .inc file in this path one level up: /project1/apps/app_rules.inc Inside app_rules.inc I'm setting the destination of where I want the binaries to be placed when built. I want all binaries to be in their respective app_type path: /project1/bin/app_typeA/ I tried using $(CURDIR) , like this: OUTPUT_PATH = /project1/bin/$(CURDIR) but instead I got the binaries buried in the entire path name like this:

I've used rake a bit (a Ruby make program), and it has an option to get a list of all the available targets, eg > rake --tasks rake db:charset # retrieve the charset for your data... rake db:collation # retrieve the collation for your da... rake db:create # Creates the databases defined in y... rake db:drop # Drops the database for your curren... ... but there seems to be no option to do this in GNU make. Apparently the code is almost there for it, as of 2007 - http://www.mail-archive.com/help-make@gnu.org/msg06434.html . Anyway, I made little hack to extract the targets from a makefile, which

I have a project which includes a code generator which generates several .c and .h files from one input file with just one invocation of the code generator. I have a rule which has the .c and .h files as multiple targets, the input file as the prerequisite, and the recipe is the invocation of the code generator. I then have further rules to compile and link the generated .c files. This works fine with a -j factor of 1, but if I increase the j factor, I find I get multiple invocations of the code generator, up to the -j factor or the number of expected target files, whichever is smallest. This