gnu-make

How to get the second dependency file using Automatic Variables in a Makefile?

时光怂恿深爱的人放手 提交于 2019-11-28 06:45:27
I need to get the nth dependency file from a rule, something similar to $n in bash. I need this because I'd like to feed in individual dependency files as options to the build program. Here's an example: dep.o: dep.src config1.cfg config2.cfg parse -cfg1 $2 -cfg2 $3 -o $@ $< Is it possible? dep.o: dep.src config1.cfg config2.cfg @echo the second preq is $(word 2,$^), the third is $(word 3,$^) 来源: https://stackoverflow.com/questions/11424204/how-to-get-the-second-dependency-file-using-automatic-variables-in-a-makefile

Makefile - compile multiple C file at once

与世无争的帅哥 提交于 2019-11-28 06:42:40
问题 This question is different from the one at makefiles - compile all c files at once in the sense that I have one extra requirement: I want to redirect all the object files in a separate directory. Here is the setup: I have multiple sources in a directory say src/mylib . I want the objects files to end up in build/mylib . Please note also that under mylib there are subdirectories. The first attempt was as follows: sources = $(shell find src/ -name ".c") objects_dirs = $(subst src/, build/, $

Compile all C files in a directory into separate programs

最后都变了- 提交于 2019-11-28 04:57:39
Is there a way using GNU Make of compiling all of the C files in a directory into separate programs, with each program named as the source file without the .c extension? Martin Broadhurst SRCS = $(wildcard *.c) PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) %: %.c $(CC) $(CFLAGS) -o $@ $< I don't think you even need a makefile - the default implicit make rules should do it: $ ls src0.c src1.c src2.c src3.c $ make `basename -s .c *` cc src0.c -o src0 cc src1.c -o src1 cc src2.c -o src2 cc src3.c -o src3 Edited to make the command line a little simpler. SRCS = $(wildcard *.c) PROGS = $(patsubst

GNU make: should the number of jobs equal the number of CPU cores in a system?

落花浮王杯 提交于 2019-11-28 03:05:28
There seems to be some controversy on whether the number of jobs in GNU make is supposed to be equal to the number of cores, or if you can optimize the build time by adding one extra job that can be queued up while the others "work". Is it better to use -j4 or -j5 on a quad core system? Have you seen (or done) any benchmarking that supports one or the other? I would say the best thing to do is benchmark it yourself on your particular environment and workload. Seems like there are too many variables (size/number of source files, available memory, disk caching, whether your source directory &

How to install and use “make” in Windows?

白昼怎懂夜的黑 提交于 2019-11-28 03:04:06
I'm following the instructions of someone whose repository I cloned to my machine. What I want is simple: to be able to use the make command as part of setting up the code environment. But I'm using Windows, and I searched online only to find a make.exe file to download, a make-4.1.tar.gz file to download (I don't know what to do with it next), and things about downloading MinGW (for GNU; but after installing it I didn't find any mention of "make"). I don't want a GNU compiler or related stuff; I only want to use "make" in Windows. Please tell me what I should do to accomplish that. Thanks in

Escaping colons in filenames in a Makefile

China☆狼群 提交于 2019-11-28 01:48:46
Is there a way to get GNU make to work correctly with filenames that contain colons? The specific problem I'm running into happens to involve a pattern rule. Here's a simplified version that does not depend on cutting and pasting tab characters: % make --version GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. This program built for x86_64-redhat-linux-gnu % cat Makefile COLON := \: all: ; true %.bar: ; cp $< $@ x.bar: x.foo %.foo:

How to manage C header file dependencies?

巧了我就是萌 提交于 2019-11-28 01:42:01
I've a lot of C files, some have a header (.h), some files not. Here's my makefile : .SUFFIXES: SRC := $(wildard ./src/*.c) OBJ := $(SRC:%.c=%.o) all: $(OBJ) %.o: %.c $(MyNotGCCCompiler) "@../$(*F).cmd" It works fine except that if I change a header file, the target isn't recompiled because not included in the dependencies. How can I manage this case? Thanks The standard approach is to generate header dependencies automatically while compiling. For the first compilation no dependencies are necessary since every source file must be compiled. Subsequent recompilations load dependencies generated

Suppress make rule error output

走远了吗. 提交于 2019-11-28 00:59:02
I have an rule that creates a directory bin: -mkdir $@ However after the first time the directory has been generated, I receive this output: mkdir bin mkdir: cannot create directory `bin': File exists make: [bin] Error 1 (ignored) Is there some way I can only run the rule if the directory doesn't exist, or suppress the output when the directory already exists? The traditional way to handle directory creation is to use a stamp file that is depended on and creates the dir as a side effect. Remove the stamp file when making distclean or whatever your "really clean" target is: bin/.dirstamp: mkdir

How to run pre- and post-recipes for every target using GNU Make?

家住魔仙堡 提交于 2019-11-28 00:56:36
问题 In make , is it possible to define a pre- and post-recipe for every target? I want to (implicitly) insert the pre-recipe just above the first line of the explicit recipe and then (implicitly) insert the post-recipe after the last line in the explicit recipe. It would be pretty easy to do it using regular expressions to insert lines but implicit ones would be so much cleaner. 回答1: You can create a special helper shell that executes the desired pre- and post- actions before and after its input

making all rules depend on the Makefile itself

こ雲淡風輕ζ 提交于 2019-11-27 22:05:57
问题 When I change a Makefile, its rules may have changed, so they should be reevaluated, but make doesn't seem to think so. Is there any way to say, in a Makefile, that all of its targets, no matter which, depend on the Makefile itself? (Regardless of its name.) I'm using GNU make. 回答1: This looks like one more simple, useful, logical thing that Make should be able to do, but isn't. Here is a workaround. If the clean rule is set up correctly, Make can execute it whenever the makefile has been