gnu-make

I have a fairly large makefile that creates a number of targets on the fly by computing names from variables. (eg foo$(VAR) : $(PREREQS)). Is there any way that gnu make can be convinced to spit out a list of targets after it has expanded these variables? I'd like to be able to get the targets for an aribitrary makefile. I'm trying to write a completion function for my shell. Can you parse the output from make -pn (i.e. make --print-data-base --dry-run )? It prints out all the variables, rules, implicit rules and which commands will be run in laborious detail. todd hodes make -qp | awk -F':' '

In my makefile, I have a variable 'NDK_PROJECT_PATH', my question is how can I print it out when it compiles? I read Make file echo displaying "$PATH" string and I tried: @echo $(NDK_PROJECT_PATH) @echo $(value NDK_PROJECT_PATH) Both gives me "build-local.mk:102: *** missing separator. Stop." Any one knows why it is not working for me? You can print out variables as the makefile is read (assuming GNU make as you have tagged this question appropriately) using this method (with a variable named "var"): $(info $$var is [${var}]) You can add this construct to any recipe to see what make will pass

I want to describe each submake's dependencies in a file that a top-level Makefile can include. This is to allows for a recursive make setup (with all of the power of instanced variables and relative pathing) but with all dependencies described in a top-level make to increase compile speed and parallelism. For instance, let's assume we have a directory tree that looks like this: project/ |-- lib1 | |-- Makefile | `-- Makefile.reg |-- lib2 | |-- Makefile | `-- Makefile.reg |-- Makefile `-- Makefile.reg The file for project/lib1/Makefile.reg file may look like this: REG := lib1 include ..