gnu-make

What is the difference between gmake and make?

主宰稳场 提交于 2019-11-28 15:20:59
问题 I am trying to understand the difference between 'gmake' and 'make'? On my linux box they are identical: % gmake --version GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. % make --version GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO

List goals/targets in GNU make that contain variables in their definition

早过忘川 提交于 2019-11-28 15:06:39
I have a fairly large makefile that creates a number of targets on the fly by computing names from variables. (eg foo$(VAR) : $(PREREQS)). Is there any way that gnu make can be convinced to spit out a list of targets after it has expanded these variables? I'd like to be able to get the targets for an aribitrary makefile. I'm trying to write a completion function for my shell. Can you parse the output from make -pn (i.e. make --print-data-base --dry-run )? It prints out all the variables, rules, implicit rules and which commands will be run in laborious detail. todd hodes make -qp | awk -F':' '

How to print out a variable in makefile

二次信任 提交于 2019-11-28 14:57:40
In my makefile, I have a variable 'NDK_PROJECT_PATH', my question is how can I print it out when it compiles? I read Make file echo displaying "$PATH" string and I tried: @echo $(NDK_PROJECT_PATH) @echo $(value NDK_PROJECT_PATH) Both gives me "build-local.mk:102: *** missing separator. Stop." Any one knows why it is not working for me? You can print out variables as the makefile is read (assuming GNU make as you have tagged this question appropriately) using this method (with a variable named "var"): $(info $$var is [${var}]) You can add this construct to any recipe to see what make will pass

Included Makefile's parent directory

六月ゝ 毕业季﹏ 提交于 2019-11-28 14:49:27
I want to describe each submake's dependencies in a file that a top-level Makefile can include. This is to allows for a recursive make setup (with all of the power of instanced variables and relative pathing) but with all dependencies described in a top-level make to increase compile speed and parallelism. For instance, let's assume we have a directory tree that looks like this: project/ |-- lib1 | |-- Makefile | `-- Makefile.reg |-- lib2 | |-- Makefile | `-- Makefile.reg |-- Makefile `-- Makefile.reg The file for project/lib1/Makefile.reg file may look like this: REG := lib1 include ..

How to call Makefile from another Makefile?

你。 提交于 2019-11-28 13:56:42
问题 I'm getting some unexpected results calling one makefile from another. I have two makefiles, one called /path/to/project/makefile and one called /path/to/project/gtest-1.4.0/make/Makefile . I'm attempting to have the former call the latter. In /path/to/project/makefile, I have dev: $(OBJ_FILES) $(CPPC) $(LIBS) $(FLAGS_DEV) $(OBJ_FILES) -o $(BIN_DIR)/$(PROJECT) $(MAKE) -f ./gtest-1.4.0/make/Makefile clean: rm -f ./*~ ./gmon.out ./core $(SRC_DIR)/*~ $(OBJ_DIR)/*.o rm -f ../svn-commit.tmp~ rm -f

Target wildcards in a shell command

冷暖自知 提交于 2019-11-28 12:50:52
问题 I'm trying to create targets that depend on a list of files in a directory with the name of the target: bin/%.out: src/%/ $(shell find src/%/* -type f -iname '*.cpp' -o -iname '*.hpp') # Build stuff here However shell find src/%/* ... ends up expanding to shell find src//* ... . At first I thought it's because I could only have 1 target wildcard but even after removing the src/%/ dependency it ended up with this same problem. Some more context: my directory contains a 'src' directory, which

googletest Undefined symbols for architecture x86_64 error

北城以北 提交于 2019-11-28 11:07:21
问题 Let GTEST_DIR be the environment variable storing the path to the googletest directory. (I cloned googletest-master from googletest's github repo.) I cd 'ed into $GTEST_DIR , did a mkdir build && cd build , then executed the following command : cmake .. -DCMAKE_C_COMPILER=$GNU-6.0.0/bin/gcc-6.0.0 -DCMAKE_CXX_COMPILER=$GNU-6.0.0/bin/g++-6.0.0 where GNU-6.0.0 is the path to my gnu install. This generated a Makefile inside $GTEST_DIR/build that I tweaked as follows : I've added CC = $GNU-6.0.0

cmake add_custom_command failure, target gets deleted

十年热恋 提交于 2019-11-28 08:36:18
问题 I am building a test executable using CMake. During the build process, I would like to run the executable, which returns whether the tests pass or not. If not, I would like the build to fail. However, when I use add_custom_command(... POST_BUILD ... ) , and use a Makefile generator, the test executable will be deleted (explain in this question: Why does GNU make delete a file). Is there a way to have CMake treat the executable as a .PRECIOUS , or otherwise change the CMakeLists.txt such that

Makefile error on windows

三世轮回 提交于 2019-11-28 07:28:27
问题 I am trying to run makefile on windows7. I have added make.exe in windows path variable and I am trying to run "make -f makefile.txt" but it shows error "cc -o edit main.o kbd.o command.o display.o insert.o search.o files.o utils.o process_begin: CreateProcess(NULL, cc -o edit main.o kbd.o command.o display.o i nsert.o search.o files.o utils.o, ...) failed. make (e=2): The system cannot find the file specified. make: *** [edit] Error" Please help me as i am new to make concept. 回答1: It is not

when multiple pattern rules match a target

喜你入骨 提交于 2019-11-28 07:03:20
问题 The GNU make manual says It is possible that more than one pattern rule will meet these criteria. In that case, make will choose the rule with the shortest stem (that is, the pattern that matches most specifically). So it surprised me that: $ touch make_specific.cpp $ cat Makefile.general_first %.o: %.cpp @echo using general rule $(CXX) -c $< -o $@ %_specific.o: %_specific.cpp @echo using specific rule $(CXX) -c $< -o $@ $ make -B -f Makefile.general_first make_specific.o using general rule g