gnu-make | 易学教程

Makefile - missing separator [duplicate]

阅读更多关于 Makefile - missing separator [duplicate]

问题 This question already has answers here : Closed 6 years ago . Possible Duplicate: Make error: missing separator Have this code in makefile: PROG = semsearch all: $(PROG) %: %.c gcc -o $@ $< -lpthread clean: rm $(PROG) and the error missing separator. stop. Can someone help me? 回答1: You need to precede the lines starting with gcc and rm with a hard tab. Commands in make rules are required to start with a tab (unless they follow a semicolon on the same line). The result should look like this:

Remove item from a Makefile variable?

阅读更多关于 Remove item from a Makefile variable?

问题 I have a makefile, which includes several other makefiles, which in turn all add to a variable like this: VAR := Something SomethingElse VAR += SomeOtherThing (...) Now I wish to remove SomethingElse from the VAR variable. What do I put in place of (...) to do this? I am using GNU Make, and a GNU Make specific solution will be fine. 回答1: You could use the filter-out text function if you're using GNU Make. OTHERVAR := $(filter-out SomethingElse,$(VAR)) 回答2: On top of the correct answer above:

How to force an error in a gnumake file

阅读更多关于 How to force an error in a gnumake file

I want to detect a condition in my makefile where a tool is the wrong version and force the make to fail with an error message indicating the item is not the right version. Can anyone give an example of doing this? I tried the following but it is not the right syntax: ifeq "$(shell svnversion --version | sed s/[^0-9\.]*://)" "1.4" $error("Bad svnversion v1.4, please install v1.6") endif Thanks. From the manual : $(error Bad svn version v1.4, please install v1.6) This will result make to a fatal error: $ make Makefile:2: *** Bad svn version v1.4, please install v1.6. Stop. While $(error...

Flat object file directory structure output with GNU Make

阅读更多关于 Flat object file directory structure output with GNU Make

I have a C++ small project using GNU Make. I'd like to be able to turn the following source files: src/ a.cpp b/ b.cpp c/ c.cpp into the following output structure (I'm not concerned about duplicates at this point): build/ a.o b.o c.o So far I have the following, which unfortunately puts the .o and .d right next to each .cpp: OBJS := $(foreach file,$(SRCS),$(file).o) DEPS := $(patsubst %.o,%.d,$(OBJS)) sinclude $(DEPS) $(OBJS) : %.o : %.cpp @echo Compiling $< $(CC) $(CC_FLAGS) $(INCS) -MMD -o $@ $< I'm aware of the $(notdir ...) function, but at this point my efforts to use it to filter the

How to manually call another target from a make target?

阅读更多关于 How to manually call another target from a make target?

I would like to have a makefile like this: cudaLib : # Create shared library with nvcc ocelotLib : # Create shared library for gpuocelot build-cuda : cudaLib make build build-ocelot : ocelotLib make build build : # build and link with the shared library I.e. the *Lib tasks create a library that runs cuda directly on the device, or on gpuocelot respectively. For both build tasks I need to run the same build steps, only creating the library differs. Is there an alternative to running make directly? make build Kind of a post-requisite? As you have written it, the build target will need to do

How to have GNU make explicitly test for failure?

阅读更多关于 How to have GNU make explicitly test for failure?

问题 After years of not using make, I find myself needing it again, the gnu version now. I'm pretty sure I should be able to do what I want, but haven't figured out how, or found an answer with Google, etc. I'm trying to create a test target which will execute my program a number of times, saving the results in a log file. Some tests should cause my program to abort. Unfortunately, my makefile aborts on the first test which leads to an error. I have something like: # Makefile # test: myProg -h >

Any interesting uses of Makefiles to share?

阅读更多关于 Any interesting uses of Makefiles to share?

问题 "make" is not only useful for building your programming project, but it seems to be under-used in other areas. For example, many shell scripts can be rewritten as Makefiles to allow independent parts to run in parallel (with "make -jXX") to keep all your CPU cores busy, with the explicitly declared dependencies as an added benefit in case you'd ever consider reordering some tasks with side effects in your shell script. Do you have any interesting stories with unusual uses of make / Makefiles

Run make in each subdirectory

阅读更多关于 Run make in each subdirectory

I have a directory ( root_dir ), that contains a number of sub-directories ( subdir1, subdir2, ... ). I want to run the make in each directory in root_dir , using a Makefile placed in it. (Obviously supposed that each of subdir... has inside its own Makefile). So there are essentially two questions: How to get a list of directories in Makefile (automatically)? How to run make for each of the directories inside a make file? As I knwow in order to run make in a specific directory I heed to do the following: $(MAKE) -C subdir There are various problems with doing the sub-make inside a for loop in

Check if a program exists from a Makefile

阅读更多关于 Check if a program exists from a Makefile

How can I check if a program is callable from a Makefile? (That is, the program should exist in the path or otherwise be callable.) It could be used to check for which compiler is installed, for instance. E.g. something like this question , but without assuming the underlying shell is POSIX compatible. Jonathan Ben-Avraham Sometimes you need a Makefile to be able to run on different target OS's and you want the build to fail early if a required executable is not in PATH rather than to run for a possibly long time before failing. The excellent solution provided by engineerchuan requires making

gnu make: list the values of all variables (or “macros”) in a particular run

阅读更多关于 gnu make: list the values of all variables (or “macros”) in a particular run

问题 How can I list the current value of all variables (also called macros) in a Makefile when running make? E.g. if this is in the Makefile: CUR-DIR := $(shell /bin/pwd) LOG-DIR := $(CUR-DIR)/make-logs Then I would like it to tell me: CUR-DIR = /home/johv/src/test LOG-DIR = /home/johv/src/test/make-logs 回答1: GNU make provides .VARIABLES which holds all global variables' names. However, this includes built-in variables(like MAKEFLAGS ). If you have to exclude built-in variables, some filtering