gnu-make

When I change a Makefile, its rules may have changed, so they should be reevaluated, but make doesn't seem to think so. Is there any way to say, in a Makefile, that all of its targets, no matter which, depend on the Makefile itself? (Regardless of its name.) I'm using GNU make. This looks like one more simple, useful, logical thing that Make should be able to do, but isn't. Here is a workaround. If the clean rule is set up correctly, Make can execute it whenever the makefile has been altered, using an empty dummy file as a marker. -include dummy dummy: Makefile @touch $@ @$(MAKE) -s clean This

In a makefile, the dependency line is of the form - abc: x y z All three of the components (x,y,z) are themselves targets in dependency lines further down in the makefile. If make abc is invoked, in what order will the three targets x,y,z be executed? Eldar Abusalimov By default, the order of execution is the same as specified in the prerequisites list, unless there are any dependencies defined between these prerequisites. abc: x y z The order is x y z . abc: x y z y : z The order would be x z y . But ideally, you should design your Makefiles so that it wouldn't rely on the order in which

We have a long and complicated Makefile in our build system. Is there a good way to trace exactly which targets get executed for a given make invocation? Use make -d or make --debug[=flags] options : ‘-d’ Print debugging information in addition to normal processing. The debugging information says which files are being considered for remaking, which file-times are being compared and with what results, which files actually need to be remade, which implicit rules are considered and which are applied—everything interesting about how make decides what to do. The -d option is equivalent to ‘--debug

I'm currently trying to build a proper Makefile. What I want is full control of what's happening, so I don't want any third party software. My current attempt seems logic to me, but since the dependency generation is not valid, I'm kind of stuck. For better readabilty, the full Makefile is broken into little pieces. I would appreciate any comment on any section if there's something to improve. First of all, I have the following static definitions CXX = g++ CXXFLAGS = -Wall \ -Wextra \ -Wuninitialized \ -Wmissing-declarations \ -pedantic \ -O3 \ -p -g -pg LDFLAGS = -p -g -pg DEPFLAGS = -MM

Is there a way to echo the (system, user, real) time spent in each target of a Makefile recursively when I do make all ? I'd like to benchmark the compilation of a project in a more granular way than just time make all . Ideally, it would echo a tree of the executed target, each one with the time spent in all its dependencies. It'd be great also if it could work with -j (parallel make). And by the way my Makefile is non-recursive (doesn't spawn another make instance for each main targets). Thanks! Gnu Make uses the $(SHELL) variable to execute commands in the targets. By default it is set to