gnu-make

问题 I would like to build a C-project for my microcontroller with the GNU make tool. I would like to do it in a clean way, such that my source code is not cluttered with object files and other stuff after the build. So imagine that I have a project folder, called \"myProject\" with two folders in it: - myProject | |---+ source | \'---+ build The build folder only contains a makefile. The figure below shows what should happen when I run the GNU make tool: So GNU make should create an object file

问题 GNU Make 3.82 gcc 4.7.2 c89 I have the following make file: INC_PATH=-I/home/dev_tools/apr/include/apr-1 LIB_PATH=-L/home/dev_tools/apr/lib LIBS=-lapr-1 -laprutil-1 RUNTIME_PATH=-Wl,-rpath,/home/dev_tools/apr/lib CC=gcc CFLAGS=-Wall -Wextra -g -m32 -O2 -D_DEBUG -D_THREAD_SAFE -D_REENTRANT -D_LARGEFILE64_SOURCE $(INC_PATH) SOURCES=$(wildcard src/*.c) OBJECTS=$(patsubst %.c, %.o, $(SOURCES)) EXECUTABLE=bin/to all: build $(EXECUTABLE) $(EXECUTABLE): $(OBJECTS) $(CC) $(CFLAGS) -o $@ $(RUNTIME

问题 I\'m trying to do this in a makefile and it fails horribly: M_ARCH := $(shell g++ -dumpmachine | awk \'{split($1,a,\"-\");print a[1]}\') do you know why? I guess it has to do with escaping, but what and where? 回答1: It's the dollar sign, in makefiles you'll have to type $$ to get a single dollar sign: M_ARCH := $(shell g++ -dumpmachine | awk '{split($$1,a,"-");print a[1]}') 回答2: Make is quite lispy when you get down to it. Here's a non-awk version that does the same thing: space := $() # M

问题 In the GNU Makefile manual, it mentions these prefixes. If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’). What do these prefixes do, and where are they mentioned? 回答1: They control the behaviour of make for the tagged command lines: @ suppresses the normal 'echo' of the command that is executed. - means ignore the exit status of the command that is executed (normally, a non-zero exit status would stop that

问题 In my GNUmakefile, I would like to have a rule that uses a temporary directory. For example: out.tar: TMP := $(shell mktemp -d) echo hi $(TMP)/hi.txt tar -C $(TMP) cf $@ . rm -rf $(TMP) As written, the above rule creates the temporary directory at the time that the rule is parsed . This means that, even I don\'t make out.tar all the time, many temporary directories get created. I would like to avoid my /tmp being littered with unused temporary directories. Is there a way to cause the variable

问题 I\'m having trouble with trying to use make to place object files in a separate subdirectory, probably a very basic technique. I have tried to use the information in this page: http://www.gnu.org/software/hello/manual/make/Prerequisite-Types.html#Prerequisite-Types I get the following output from make: make: *** No rule to make target `ku.h\', needed by `obj/kumain.o\'. Stop. However ku.h is a dependency not a target (although it\'s obviously #included within the c source files). When I don\

问题 It\'s been a while since I\'ve used make , so bear with me... I\'ve got a directory, flac , containing .FLAC files. I\'ve got a corresponding directory, mp3 containing MP3 files. If a FLAC file is newer than the corresponding MP3 file (or the corresponding MP3 file doesn\'t exist), then I want to run a bunch of commands to convert the FLAC file to an MP3 file, and copy the tags across. The kicker: I need to search the flac directory recursively, and create corresponding subdirectories in the

问题 I use CMake with GNU Make and would like to see all commands exactly (for example how the compiler is executed, all the flags etc.). GNU make has --debug , but it does not seem to be that helpful are there any other options? Does CMake provide additional flags in the generated Makefile for debugging purpose? 回答1: When you run make, add VERBOSE=1 to see the full command output. For example: cmake . make VERBOSE=1 Or you can add -DCMAKE_VERBOSE_MAKEFILE:BOOL=ON to the cmake command for

问题 Can anybody give a clear explanation of how variable assignment really works in Makefiles. What is the difference between : VARIABLE = value VARIABLE ?= value VARIABLE := value VARIABLE += value I have read the section in GNU Make\'s manual, but it still doesn\'t make sense to me. 回答1: Lazy Set VARIABLE = value Normal setting of a variable - values within it are recursively expanded when the variable is used, not when it's declared Immediate Set VARIABLE := value Setting of a variable with