Force gnu make to rebuild objects affected by compiler definition

问题

I have a makefile that takes options at the command line

make OPTION_1=1

Based on the value it will add additional compiler definitions to a subset of objects.

ifeq ($(OPTION_1), 1)
CC_FLAGS += -DOPTION_1_ON
endif

The change in the definition affects the included header file content - a stub or an implementation is exposed to the object files.

How can I get make to rebuild the files 'affected' by this option changing?

回答1:

I use a file to remember the last value of such options, like this:

.PHONY: force
compiler_flags: force
    echo '$(CC_FLAGS)' | cmp -s - $@ || echo '$(CC_FLAGS)' > $@

The cmp || echo bit means the file compiler_flags is only touched when the setting changes, so now you can write something like

$(OBJECTS): compiler_flags

to cause a rebuild of $(OBJECTS) whenever the compiler flags change. The rule for compiler_flags will be executed every time you run make, but a rebuild of $(OBJECTS) will be triggered only if the compiler_flags file was actually modified.

回答2:

put them in a target then call touch on each file.

来源：https://stackoverflow.com/questions/3236145/force-gnu-make-to-rebuild-objects-affected-by-compiler-definition