gnu-make

How do you implement a Makefile that remembers the last build target?

对着背影说爱祢 提交于 2019-11-30 05:16:24
问题 Let's say you have a Makefile with two pseudo-targets, 'all' and 'debug'. The 'debug' target is meant to build the same project as 'all', except with some different compile switches (like -ggdb, for example). Since the targets use different compile switches, you obviously need to rebuild the entire project if you switch between the two. But GNUmake doesn't naturally recognize this. So if you type make all you'll get Building ... ... Then if you type make debug , you get make: Nothing to be

Order-only prerequisites not working correctly in GNU make?

时光总嘲笑我的痴心妄想 提交于 2019-11-30 04:54:57
I have a problem with order-only prerequisites. These do not execute first at all. Am I mis-understanding the way order-only prerequisites work? The following make script: .PHONY: mefirst mefirst2 mefirst: @echo "I'm first!" mefirst2: @echo "I'm first too!" normaltarget: normaltarget2 | mefirst2 @echo "normaltarget done" normaltarget2: a b c @echo "normaltarget2 done" helloworld: normaltarget | mefirst @echo "helloworld done" .DEFAULT_GOAL := go go: helloworld @echo "go done" a: @echo a b: @echo b c: @echo c ...prints out the following: a b c normaltarget2 done I'm first too! normaltarget done

Makefile profiling

不打扰是莪最后的温柔 提交于 2019-11-30 02:19:58
So I have this Makefile based build system that my users feel is working too slowly. For the sake of this question lets define performance as the time it takes make to figure out what it should actually do. I can see some avenues for optimization -- Reducing the number of times Makefile is parsed and the DAG recalculated due to including a Makefile fragment. Reducing the number of going to an external Makefile with make -C Reducing variable expansions etc. -- however I want to know first where are my bottlenecks. Since optimization without profiling is a waste of life, I want to ask: How to

forcing order of prerequisites in Makefiles

血红的双手。 提交于 2019-11-30 01:15:14
问题 I have a third party makefile, and I'd like one of the targets (T1) to not be built until another, custom target (T2) is built first. Normally, this would be accomplished by making T2 a prerequisite of T1. BUT, T1 uses the $^ in one of its rules.. so, by adding the prerequisite, I end up breaking the build... What I have is this: T1: x y z T2 $(MAKE) -j $^; # fails because T2 should not be passed to the make!!! .PHONY: T2 T2: #do some linking and prep for T1 Is there a good way to ensure that

How to specify RPATH in a makefile?

你离开我真会死。 提交于 2019-11-29 23:57:29
I'm trying to specify rpath in my binary. My makefile looks like this- CC=gcc CFLAGS=-Wall LDFLAGS= -rpath='../libs/' main: main.c gcc -o main main.c clean: rm -f main main.o But when I query rpath using command readelf -a ./main | grep rpath I get nothing I've tried specifying rpath as LDFLAGS= "-rpath=../libs/" but even that doesn't seem to work. Can someone please post an example on how should I specify rpath in a makefile? GCC and ld versions are- gcc (Ubuntu/Linaro 4.5.2-8ubuntu4) 4.5.2 GNU ld (GNU Binutils for Ubuntu) 2.21.0.20110327 If you set the variables, you should probably use them

Remove item from a Makefile variable?

走远了吗. 提交于 2019-11-29 22:45:58
I have a makefile, which includes several other makefiles, which in turn all add to a variable like this: VAR := Something SomethingElse VAR += SomeOtherThing (...) Now I wish to remove SomethingElse from the VAR variable. What do I put in place of (...) to do this? I am using GNU Make, and a GNU Make specific solution will be fine. Mat You could use the filter-out text function if you're using GNU Make. OTHERVAR := $(filter-out SomethingElse,$(VAR)) On top of the correct answer above: VAR = bla1 bla2 bla3 bla4 bla5 TMPVAR := $(VAR) VAR = $(filter-out bla3, $(TMPVAR)) all: @echo "VAR is: $(VAR

Makefile - missing separator [duplicate]

有些话、适合烂在心里 提交于 2019-11-29 22:45:47
Possible Duplicate: Make error: missing separator Have this code in makefile: PROG = semsearch all: $(PROG) %: %.c gcc -o $@ $< -lpthread clean: rm $(PROG) and the error missing separator. stop. Can someone help me? You need to precede the lines starting with gcc and rm with a hard tab. Commands in make rules are required to start with a tab (unless they follow a semicolon on the same line). The result should look like this: PROG = semsearch all: $(PROG) %: %.c gcc -o $@ $< -lpthread clean: rm $(PROG) Note that some editors may be configured to insert a sequence of spaces instead of a hard tab

Target-specific variables in a makefile & prerequisites

时光毁灭记忆、已成空白 提交于 2019-11-29 20:33:37
问题 I'm seeing unexpected results for target-specfic variables in GNU make. What I want is to set a target-specific variable that affects dependencies. I can use .SECONDEXPANSION to achieve that. some-target: DEP := debug-dep debug: some-target .SECONDEXPANSION: some-target: $$(DEP) @echo $^ debug-dep: make debug prints debug-dep . Now I read that make defines target-specific variables for descendant rules: When you define a target-specific variable that variable value is also in effect for all

How to use GNU Make on Windows?

好久不见. 提交于 2019-11-29 18:58:43
I installed MinGW and MSYS, added C:\MinGW\bin to PATH but I still can't run Makefile on Windows' cmd . I would like to run cmd.exe and there type, for example, make all but my cmd says that there is no such command. What should I do? I don't want to use MSYS shell, that's not the point. Any ideas how to use GNU Make in Windows cmd as I can do it in Ubuntu? I'm not interested in Cygwin . Here's how I got it to work: copy c:\MinGW\bin\mingw32-make.exe c:\MinGW\bin\make.exe Then I am able to open a command prompt and type make: C:\Users\Dell>make make: *** No targets specified and no makefile

How can I configure my makefile for debug and release builds?

萝らか妹 提交于 2019-11-29 18:33:33
I have the following makefile for my project, and I'd like to configure it for release and debug builds. In my code, I have lots of #ifdef DEBUG macros in place, so it's simply a matter of setting this macro and adding the -g3 -gdwarf2 flags to the compilers. How can I do this? $(CC) = g++ -g3 -gdwarf2 $(cc) = gcc -g3 -gdwarf2 all: executable executable: CommandParser.tab.o CommandParser.yy.o Command.o g++ -g -o output CommandParser.yy.o CommandParser.tab.o Command.o -lfl CommandParser.yy.o: CommandParser.l flex -o CommandParser.yy.c CommandParser.l gcc -g -c CommandParser.yy.c CommandParser