gnu-make

What setup works for GNU make parallel jobs (-j) on Windows? I have tried setting the shell to cmd.exe using MinGW make 3.81, this works in creating the multiple processes but make fails with the "waiting for job" message. Can this work and what is the best setup? (MinGW / Cygwin / ???) Can someone point me to a working example to test against? I've never had any promblems using make -jn under Cygwin. It works rather well. I regularly use it with Microsoft's cl.exe compiler. It just works out of the box for me. Very UNIX like, which is a Good Thing™. Build scripts port nicely to Linux and the

Is there a way to remove a prefix from a string (a pathname in my case) in make ? As an example, suppose I had the string: FILES = a/b/c.d a/b/e.f I want to remove the a/ , and be left with b/c.d b/e.f I have tried using various combinations of dir , notdir and basename from the GNU make manual , but none seem to provide a nice solution. $(dir $(FILE)) # a/b a/b $(notdir $(FILE)) # c.d e.f $(basename $(FILE)) # a/b/c a/b/e The only way I've found to do this so far is: $( join $(basename $(dir $(FILE))), $(notdir $(FILE)) ) Which is really ugly and long-winded. What I really need is some kind

How similar/different are gnu make, microsoft nmake and posix standard make? Obviously there's things like "which OS?", "which compiler?" and "which linker?", but I'm referring specifically to the syntax, semantics and command-line options of the makefiles themselves. If I write makefiles based on manuals for gnu make, what are the most important portability issues that I need to be aware of? GNU Make and POSIX Make share a common core so that GNU Make understands makefiles intended for POSIX Make and interprets them the same way - with very few exceptions. However, many GNU Makefiles use

In my Makefile, I need to test if the current directory is an SVN repo or not and if it is not I want to indicate an error using the $(error) directive in Makefile. So I plan to use the return value of $(shell svn info .) but I'm not sure how to get this value from within the Makefile. Note: I'm not trying to get the return value in a recipe, but rather in the middle of the Makefile. Right now I'm doing something like this, which works just because stdout is blank when it is an error: SVN_INFO := $(shell svn info . 2> /dev/null) ifeq ($(SVN_INFO),) $(error "Not an SVN repo...") endif I'd still

How do I make this work? It errors out with "make: somevariable: Command not found" sometarget: somevariable = somevalue Full example: CXXFLAGS = -I/usr/include/test -shared -fPIC OBJ = main.o Server.o blabla : $(OBJ) ifeq ($(argsexec),true) # Creates an executable CXXFLAGS = -I/usr/include/test $(CXX) -o blabla $(OBJ) $(CXXFLAGS) else # Creates a library DESTDIR = /home/pc $(CXX) -o blabla $(OBJ) $(CXXFLAGS) ./bn.sh endif Blub I found a solution using the eval function : $(eval variablename=whatever) This works :) (although I may now try to find an easier build system ;)) Thanks everyone for

I'm trying to compile the following program in Ubuntu. But I keep getting the error: "stdio.h: No such file or directory" error. #include <stdio.h> int main(void) { printf("Hello world"); } My makefile is: obj-m += hello.o all: make -I/usr/include -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean Your way of building your program is the way to build kernel module and not c program application. and stdio.h does not exist in the environment of the kernel development so that's why you get the error: error: "stdio.h: No such

I'm expecting to see files foo1 and foo3 created by the makefile below. However only a file foo3 is created. To me it seems that the canned recipe make-foo is simply ignored by make. The debug outcome of targets foo1 and foo2 (empty recipe) is identical. # why canned recipe doesn't work ? # http://www.gnu.org/software/make/manual/make.html#Canned-Recipes define make-foo = echo making $@ touch $@ endef .PHONY: all all: foo1 foo2 foo3 # foo1 is not created, but why ? .PHONY: foo1 foo1: $(make-foo) # debug output similar to foo1 .PHONY: foo2 foo2: # this works .PHONY: foo3 foo3: echo making $@

Is it possible to suppress command echoing by default from within the Makefile ? I know that running make in --silent mode will do it, as will prefixing every command with @ . I'm looking for a command or stanza I can include inside the Makefile, saving the trouble of littering everything with @ or having the user silence everything manually. Chris Dodd If you define the target .SILENT: , then make will not echo anything. It's usually best to guard the definition, so you can easily turn it off: ifndef VERBOSE .SILENT: endif Now by default, make will print nothing, but if you run make VERBOSE=1