gnu-make

For the following make file copied below, I am getting the missing separator error. Nothing seems to be wrong with the tabspace. OBJS = driver.o snapshot.o SHOBJS = malloc.o mymemory.o CC = g++ DEBUG = -g CFLAGS = -Wall -c $(DEBUG) LFLAGS = -Wall $(DEBUG) Snapshot: $(OBJS) $(CC) $(LFLAGS) $(OBJS) -o Snapshot driver.o: snapshot.h driver.cpp $(CC) $(CFLAGS) driver.cpp snapshot.o: mymemory.h snapshot.h snapshot.cpp $(CC) $(CFLAGS) snapshot.cpp libmymemory.so: $(SHOBJS) gcc -shared -o libmymemory.so malloc.o mymemory.o malloc.o: malloc.c gcc -fPIC -g -c -Wall malloc.c mymemory.o: mymemory.cpp gcc

From the documentation for GNU make: http://www.gnu.org/software/make/manual/make.html#Parallel When the system is heavily loaded, you will probably want to run fewer jobs than when it is lightly loaded. You can use the ‘-l’ option to tell make to limit the number of jobs to run at once, based on the load average. The ‘-l’ or ‘--max-load’ option is followed by a floating-point number. For example, -l 2.5 will not let make start more than one job if the load average is above 2.5. The ‘-l’ option with no following number removes the load limit, if one was given with a previous ‘-l’ option. More

This is a "Hello.c" module and "Makefile". After executing make from the woking directory I get the following message: make: Nothing to be done for `all'. This is the "Hello.c" file: #include <linux/module.h> // included for all kernel modules #include <linux/kernel.h> // included for KERN_INFO #include <linux/init.h> // included for __init and __exit macros MODULE_LICENSE("GPL"); MODULE_AUTHOR("Lakshmanan"); MODULE_DESCRIPTION("A Simple Hello World module"); static int __init hello_init(void) { printk(KERN_INFO "Hello world!\n"); return 0; // Non-zero return means that the module couldn't be

(edit: question more accurate based on @Michael feedback) In bash, I often use parameter expansion : the following commands print " default value " when $VARNAME is unset, otherwise it prints the VARNAME content. echo ${VARNAME:-default value} #if VARNAME empty => print "default value" echo ${VARNAME-default value} #if VARNAME empty => print "" (VARNAME string) I did not find a similar feature on GNU make . I finally wrote in my Makefile : VARNAME ?= "default value" all: echo ${VARNAME} But I am not happy with this solution: it always creates the variable VARNAME and this may change the