gnu-make

I want to use GNUMake to run a rule-based makefile which builds a set of C files in a directory structure (on a Windows file system). The root directory, some sub-directories and some files contain spaces. Example file: "C:\Documents and Settings\<username>\My Documents\Test Dir\Build Me.c" GNUMake doesn't really work when the file paths contain spaces. I've read about the possible ways of working around this issue (removing the spaces from my filenames, using the 8.3 format, substituting spaces with ? or \\ etc.) but none of them are perfect (or are they?) Is there a silver bullet that will

I am trying to compile this tool. Below is the beginning of its Makefile: CC = gcc CFLAGS = -Wall -O2 -D TRACES DFLAGS = -g -Wall -o0 CPPFLAGS= $(INCLUDES:%=-I %) LDFLAGS = $(LIBRARIES:%=-L %) LDLIBS = $(USED_TOOLS:%=-l%) MY_FILES = INCLUDE_DIR = ~/include TOOLBOX_INC = $(INCLUDE_DIR)/tools TOOLBOX_LIB = $(TOOLBOX_INC) USED_TOOLS = std_io stringutils INCLUDES = $(TOOLBOX_INC) LIBRARIES = $(TOOLBOX_LIB) I also have ~/include/tools which after compiling includes std_io.o, libstd_io.a, stringutils.o and libstringutils.a I am getting the following error: gcc -L ~/include/tools rank.o

I have a GNU Makefile that looks a bit like this: LIST = item1 .PHONY: targetMain targetA targetB preA preB targetMain: # DO all the work in here echo $(LIST) targetA: preA targetMain targetB: preB targetMain preA: LIST += itemA preB: LIST += itemB The idea is that I either run make targetA or make targetB. Both of them do a very similar thing, but with a different list of items. The problem is that the variable isn't conditionally appended to, it is always appended to, meaning my output is always "item1 itemA itemB". How can I conditionally append to a variable? LIST = item1 .PHONY:

Let's say you have a Makefile with two pseudo-targets, 'all' and 'debug'. The 'debug' target is meant to build the same project as 'all', except with some different compile switches (like -ggdb, for example). Since the targets use different compile switches, you obviously need to rebuild the entire project if you switch between the two. But GNUmake doesn't naturally recognize this. So if you type make all you'll get Building ... ... Then if you type make debug , you get make: Nothing to be done for `debug'. So my question is: how do you implement a clean solution in the Makefile to notice that

When i try to $ make depend -f gcc.mak a middleware on my Ubuntu machine I get this /usr/include/../include/limits.h:125:26: error: no include path in which to search for limits.h This is the contents around limits.h:125: /* Get the compiler's limits.h, which defines almost all the ISO constants. We put this #include_next outside the double inclusion check because it should be possible to include this file more than once and still get the definitions from gcc's header. */ #if defined __GNUC__ && !defined _GCC_LIMITS_H_ /* `_GCC_LIMITS_H_' is what GCC's file defines. */ # include_next <limits.h

I have a third party makefile, and I'd like one of the targets (T1) to not be built until another, custom target (T2) is built first. Normally, this would be accomplished by making T2 a prerequisite of T1. BUT, T1 uses the $^ in one of its rules.. so, by adding the prerequisite, I end up breaking the build... What I have is this: T1: x y z T2 $(MAKE) -j $^; # fails because T2 should not be passed to the make!!! .PHONY: T2 T2: #do some linking and prep for T1 Is there a good way to ensure that T2 is run before T1? (Note: the above example is actually simplified by a bit. T1 is actually the