I have a third party makefile, and I'd like one of the targets (T1) to not be built until another, custom target (T2) is built first. Normally, this would be accomplished by making T2 a prerequisite of T1. BUT, T1 uses the $^ in one of its rules.. so, by adding the prerequisite, I end up breaking the build... What I have is this:
T1: x y z T2
$(MAKE) -j $^;
# fails because T2 should not be passed to the make!!!
.PHONY: T2
T2:
#do some linking and prep for T1
Is there a good way to ensure that T2 is run before T1? (Note: the above example is actually simplified by a bit. T1 is actually the vmlinux target within the Linux kernel makefile, so rewriting it is not only difficult, it makes the code non-portable. Also, I can't run T2 before calling make on the kernel due to some other dependencies).
Have T2 as an order-only prerequisite:
T1: x y z | T2
$(MAKE) -j $^;
# Make will run the T2 rule before this one, but T2 will not appear in $^
Could you just call Make in your build script with the two targets in the proper order, e.g.
make T2 T1
That way you don't need to make any modifications to T1.
来源：https://stackoverflow.com/questions/14267123/forcing-order-of-prerequisites-in-makefiles