fpga

问题 I used the following code to instantiate 2-D memory in a verilog reg [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF}; reg [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF}; This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done Can anyone elaborate to me as in how that is possible? 回答1: For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software

问题 I am adapting a Windows / Linux driver of a FPGA based PCIe card. (using a LatticeECP3 with PCIe Endpoint) I need to add a driver function to allow a host driven bitstream update of the FPGA without the need of rebooting the host afterwards. I.e. after flashing I would need to reset the FPGA to let the bitstream be reloaded. This of course would lead to a loss of the Config Space settings of PCIe endpoint. My first approach was to implement following steps: Save the PCI config space of the

问题 I'm trying to do a VHDL code with the objective to make a 8 bit LFSR and show all the random states, and after one cycle (when the last state be the same seed value) it stop. But I'm have a problems, keep saying: "loop must terminate within 10,000 iterations". I'm using Quartus II-Altera. Code: entity lfsr_8bit is --generic ( n : integer := 2**8 ); port ( clk : in bit; rst : in bit; lfsr : out bit_vector(7 downto 0) ); end lfsr_8bit; architecture behaviour of lfsr_8bit is --signal i : integer

问题 I am trying to simulate my VHDL file, but am running into the following error: # ** Error: (vcom-11) Could not find work.lab1. # # ** Error: (vcom-1195) Cannot find expanded name "work.lab1". # # ** Error: Unknown expanded name. # ** Error: VHDL Compiler exiting # ** Error: c:/altera/12.1/modelsim_ase/win32aloem/vcom failed. # Error in macro ./DE2_TOP_run_msim_rtl_vhdl.do line 8 # c:/altera/12.1/modelsim_ase/win32aloem/vcom failed. # while executing # "vcom -93 -work work" I compiled the code

问题 Chisel generate always blocks with only clock in sensivity list : always @posedge(clk) begin [...] end Is it possible to configure Module to use an asynchronous reset and generate an always block like this ? always @(posedge clk or posedge reset) begin [...] end 回答1: It looks like this question has been asked elsewhere on the interwebs... the answer is that Chisel does not natively have this functionality built into it. It looks like the way to do this in Chisel is to use synchronous resets:

问题 I am currently trying to develop a Sobel filter in VHDL. I am using a 640x480 picture that is stored in a BRAM. The algorithm uses a 3x3 matrix of pixels of the image for processing each output pixel. My problem is that I currently only know of putting an image into a BRAM where each address of the BRAM holds one pixel value. This means I can only read one pixel per clock. My problem is that I am trying to pipeline the data so I would ideally need to be able to get three pixel values (one

问题 I seem to be under the impression that FPGAs can be updated while the chip is running; and I need to know if that is correct or not. It seems to be from what I've read that you can change the FPGA netlist on demand the same way you can change the program that's running on a processor. Yes I know that an FPGA is not a processor. Is my assumption correct, and if not then how come? 回答1: Most of the time, you load the configuration for the entire FPGA in one go, and all logic stops running during

问题 I have a very simple FSM which should drive some output signals of an external RAM. The problem that I have comes with handling the data bus which can be input as well as output... I am not too sure how I can handle best this case in my FSM. The problem comes from the following line: v.sram_data <= io_sram_data; Obviously, the left hand side is a variable while the right hand side is a signal. Is there a "nice" way how to handle inout signals in a FSM as the one I have? entity sram_fsm is

问题 I am trying to send a 4 kilobyte string to an FPGA, what is the easiest way that this can be done? This is the link for the fpga that I am using. I am using Verilog and Quartus. 回答1: The answer to your question depends a lot on what is feeding this data into the FPGA. Even if there isn't a specific protocol you need to adhere to (SPI, Ethernet, USB, etc.), there is the question of how fast you need to accept the data, and how far the data has to travel. If it's very slow, you can create a