Trying to show one cycle of 8 bit LFSR with VHDL

问题

I'm trying to do a VHDL code with the objective to make a 8 bit LFSR and show all the random states, and after one cycle (when the last state be the same seed value) it stop. But I'm have a problems, keep saying: "loop must terminate within 10,000 iterations". I'm using Quartus II-Altera.

Code:

entity lfsr_8bit is
    --generic ( n : integer := 2**8 );
    port (
        clk : in bit;
        rst : in bit;
        lfsr : out bit_vector(7 downto 0)
    );
end lfsr_8bit;

architecture behaviour of lfsr_8bit is
    --signal i : integer := 0;
    --signal seed : bit_vector(7 downto 0) := "10000000";
    signal rand : bit_vector(7 downto 0);
begin
    ciclo : process (clk,rst)
    begin
        loop
            if (rst='0') then
                rand <= "10000000";
            elsif (clk'event and clk='1') then
                rand(0) <= rand(6) xor rand(7);
                rand(7 downto 1) <= rand(6 downto 0);
            end if;

            -- wait until rand = "10000000" for 100 ns;
            exit when rand = "10000000";

            --      case rand is
            --      when "10000000" => EXIT;
            --      when others     => NULL;
            --      end case;
            --  i <= i +1;
        end loop;
        lfsr <= rand(7 downto 0);
    end process ciclo;
end behaviour;

Thank you for all help.

回答1:

Get rid of that loop, that loop does not work the way you think it does! Stop thinking like a software designer and think like a hardware designer. Loops in hardware are used to replicate logic. So that loop of yours is literally trying to generate 10,000 LFSRs!

I don't believe that you need to be using that loop there at all. If you remove it your LFSR should work as intended. You may need to add a control signal to enable/disable the LFSR, but definitely do not use a loop.

Here's some example code demonstrating this. Change the default value of rand to something else or the LFSR will never run! It will immediately set the lfsr_done signal.

ciclo : process (clk,rst)
begin
if (rst='0') then
    rand      <= "10000000";  -- SET THIS TO SOMETHING DIFFERENT
    lfsr_done <= '0';
elsif (clk'event and clk='1') then
    if rand = "10000000" then
       lfsr_done <= '1';
    end if;

    if lfsr_done = '0' then
        rand(0) <= rand(6) xor rand(7);
        rand(7 downto 1) <= rand(6 downto 0);
    end if;
end if;

来源：https://stackoverflow.com/questions/25016926/trying-to-show-one-cycle-of-8-bit-lfsr-with-vhdl

标签

vhdl

fpga