How to generate an asynchronous reset verilog always blocks with chisel

问题

Chisel generate always blocks with only clock in sensivity list :

always @posedge(clk) begin
  [...]
end

Is it possible to configure Module to use an asynchronous reset and generate an always block like this ?

always @(posedge clk or posedge reset) begin
   [...]
end

回答1:

It looks like this question has been asked elsewhere on the interwebs... the answer is that Chisel does not natively have this functionality built into it.

It looks like the way to do this in Chisel is to use synchronous resets:

always @posedge(clk) begin
  if (reset) begin
  [...]
  end 
  else 
  [...]
  end
end

For more discussion on the topic: https://groups.google.com/forum/#!topic/chisel-users/4cc4SyB5mk8

来源：https://stackoverflow.com/questions/29767059/how-to-generate-an-asynchronous-reset-verilog-always-blocks-with-chisel