fpga

问题 In a module I would like to make many registers of varying length, and send information between those registers each clock cycle. Specifically, I am trying to create a module which adds all the elements in a list efficiently by adding their elements pairwise into a new list, then continuing until there is one element. Something like the following, where the input represents 4 lists of length 16 of 8 bit integers (this code passes synthesis and implementation, although I have not tested it so

问题 In the below module, ideally cnt, width & start should be inout port, instead of output port. But I tried with those ports as output ports and still I am able to run it without any error. So can inout and output ports be used interchangeably in Verilog? If no, then what is the exact criteria, where inout port must be used (output port can't be used in that case)? module (clk, rst, cnt, start, width, signal); input clk, rst, signal; output reg [11:0] cnt, width; output reg start; always @

问题 I initialize a register reg[1:0] yreg; and manipulate it a bit, i.e., value from prev. iteration of program is shifted to 1 spot when I add in the new value in the 0 spot yreg = SIGNAL; //here SIGNAL is an input to the program And then I want to access the values at the 0 and 1 spots in the register later for a calculation. How can I do this? My initial reaction was yreg[0] and yreg[1] (I normally program in python =) but this is producing an error (line 35 is the line of code that has yreg[0

问题 I have the Xilinx Spartan6 and next VHDL code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Switches_Leds is Port (switch_0: in STD_LOGIC; LED_0 : out STD_LOGIC); end Switches_Leds; architecture Behavioral of Switches_Leds is begin LED_0 <= switch_0; end; Here is my User constraint file: NET "switch_0" LOC = C3; NET "LED_0" LOC = P4; My question is: Why the led is always is turned on, but it goes off if I click on button ? I explain: I program my fpga - the led

问题 I looked in the manual (page 177) for the DE2 and as far as I understand it should be possible to do serial communication for instance via putty and a usb-to-serial cable to the board, so I take the program from the manual: /* A simple program that recognizes the characters 't' and 'v' */ #include <stdio.h> #include <string.h> int main () { char* msg = "Detected the character 't'.\n"; FILE* fp; char prompt = 0; fp = fopen ("/dev/uart1", "r+"); //Open file for reading and writing if (fp) {

问题 I would like to write an integer (variable num) on a file (write.txt). Here my code but obviously it does not work. Any suggestion? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; library std; use std.textio.all; entity file_handle is end file_handle; architecture Behavioral of file_handle is begin process variable line_var : line; file text_var : text; variable num : integer := 40; begin file_open(text_var,"C:\Users\Tommy\Desktop\write.txt", write_mode); write(line_var,

问题 I am trying to convert the input word coming out of the DQPSK Demodulator (Type : UFix2_0) to a serial stream. So I am using the Parallel-to-Serial Block of Xilinx Library in Simulink. But I am not able to use the block, I get the following error : "The Simulink system period" setting on this System Generator token is not appropriate for the rates used in the design. The current setting is: 1 An appropriate setting is: 1/2 " I tried to change the setting the System Generator as well, but It

问题 I'm trying to implement a simple verilog code as below: module test1( input ACLK, input RST, output test_output1, output test_output2 ); //wire ACLK; //wire RST; reg test_output1; reg test_output2; assign test_output1 = ACLK; always @(posedge ACLK or negedge RST) begin if(!RST) begin //test_output1 <=0; test_output2 <=0; end else begin //test_output1 <=0; test_output2 <=1; end end endmodule I get the following error message when I try to synthesize it in Xilinx ISE: ==========================

问题 I have a error while Synthesize this code in Xillinx. This error is: Analyzing Entity in library (Architecture ). ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description. entity Parking is port( A, B ,reset: in std_logic; Capacity : out std_logic_vector(7 downto 0)); end Parking; architecture Behavioral of Parking is type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout); signal current, nxt :

问题 I'm trying to simulate ICE5LP1K FPGA internal oscillator on ModelSim. My design includes the following instance: SB_HFOSC OSCInst1 ( .CLKHFEN(1'b1), .CLKHFPU(1'b1), .CLKHF(CLKLF) ) I included sb_ice_syn.v file but have a design loading error: Error: ../testbench/sb_ice_syn.v(26066): Module 'SB_HFOSC_CORE' is not defined I'm not able to find SB_HFOSC_CORE module in the lattice installation folder. Where can I find the missed modules? 回答1: Doing ModelSim simulation of a Lattice ICE40 family