fpga

问题 I am implementing an FSM controller for a datapath circuit. The controller increments a counter internally. When I simulated the program below, the counter was never updated. reg[3:0] counter; //incrementing counter in combinational block counter = counter + 4'b1; However, on creating an extra variable, counter_next, as described in Verilog Best Practice - Incrementing a variable and incrementing the counter only in the sequential block, the counter gets incremented. reg[3:0] counter, counter

问题 What is it called the thread of execution on the FPGA (Xilinx Virtex 5/7), and how many number of its can be theoretically (minimum and maximum)? 回答1: FPGAs are reprogrammable circuits, and the components of those circuits are always running in parallel. The concept of threads from software development and multi-threaded processors do not apply to hardware design on an FPGA. If you define a "thread" as a unit of computation that can operate in parallel from other units, you could say an FPGA

问题 (I'd post this in EE but it seems there are far more VHDL questions here...) Background: I'm using the Xilinx Spartan-6LX9 FPGA with the Xilinx ISE 14.4 (webpack). I stumbled upon the dreaded "PhysDesignRules:372 - Gated clock" warning today, and I see there's a LOT of discussion out there concerning that in general. The consensus seems to be to use one of the DCMs on the FPGA to do clock division but... my DCM doesn't appear to be capable of going from 32 MHz to 4.096 KHz (per the wizard it

问题 I'm trying to make a morse code display using an led. I need a half second pulse of the light to represent a dot and a 1.5 second pulse to represent a dash. I'm really stuck here. I have made a counter using an internal 50MHz clock on my FPGA. The machine I have to make will take as input a 3 bit number and translate that to a morse letter, A-H with A being 000, B being 001 and so on. I just need to figure out how to tell the FPGA to keep the led on for the specified time and then turn off

问题 I want to use four push buttons as inputs and three seven-segment LED displays as outputs. Two push buttons should step up and down through the sixteen RAM locations; the other two should increment and decrement the contents of the currently-displayed memory location. I am now trying to simulate my design using ModelSim test benches, with button presses. Here is what I believe to be the relevant portions of my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

问题 I'm a beginner to vhdl. I am trying to write a VHDL code to describe the behavior of a traffic light. It has 3 signal outputs Yellow (0), Green (1) and Red (2). Initially the light is yellow. It would be turning to Green after 10ns. Green would turn to red after 40ns and red would come back to yellow after 60ns. The state machine is not having any external input and is a free running machine synchronized by a 10ns clock (total time period = 10ns). Traffic light has an external reset control

问题 I have never come across this problem before when uses black-boxes inside custom IP. Usually I instantiate and add the custom IP to the project, and then instantiate and add the black box IP modules (the black boxes are inside the custom IP) to the project. For some reason now I am getting the classic [Project 1-486] Could not resolve non-primitive black box cell 'FX_Thomas_Core_0FX_Thomas_Core_0FX_Thomas_Core_0Thomas_Sub' instantiated as 'Subtractor' ["c:/Users/Sam/Documents/Zynq7020/FX

问题 pollkey() should be called every millisecond and tick(&timeloc) should be called every second and I don't have a thread library. The obvious way would be to do it with threads but now it seems that I need advice how to perform both the updates. The code I'm trying is int main() { while (TRUE) { pollkey(); puttime(&timeloc); delay(1); IOWR_ALTERA_AVALON_PIO_DATA(DE2_PIO_REDLED18_BASE, timeloc); if (RUN == 1) { tick(&timeloc); puthex(timeloc); } } return 0; } But I don't think that the above is

问题 code of booth multiplier is :- module ni(prod, a, b, busy, mc, mp, clk, start); output [15:0] prod; output [7:0] a, b; output busy; input [7:0] mc, mp; input clk, start; reg [7:0] A, Q, M; reg Q_1; reg [3:0] count; wire [7:0] sum, difference; always @(posedge clk) begin if (start) begin A <= 8'b0; M <= mc; Q <= mp; Q_1 <= 1'b0; count <= 4'b0; end else begin case ({Q[0], Q_1}) 2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q}; 2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q}; default: {A, Q, Q_1}

问题 Recently I asked here, how to generate random numbers in hardware and was told to use an LFSR. It will be random but will start repeating after a certain value. The problem is that the random numbers generated are so predictable that the next value can be easily guessed. For example check the simulation below: The next "random" number can be guessed by adding the previous number with a +1 of itself. Can someone please verify if this is normal and to be expected. Here is the code I used for