fpga | 易学教程

How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

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问题 Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function* ......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation .. module state_delay; reg

VHDL equivalent for Verilog @(posedge clk) [closed]

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问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 4 years ago . I am not familiar with verilog. I did my best trying to convert it. While simulating the clock is going from '0' to 'x' which is weird. I am suspecting this part to be the problem repeat(9) @(posedge clk); DataIn_i <= 1'b1; DataIn_q <= 1'b1; @(posedge clk); FillSel <= 1'b0; DataIn_i <= 1'b0; DataIn_q <= 1'b0;

Frequency of Montgomery Multiplier

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问题 I have designed a 16*16 Montgomery multiplier. The code uses a 16*16 multiplier to perform three multiplications. The multiplications are performed one after the other using the same multiplier and the result of each multiplication is stored in the registers. The single 16*16 multiplier performs at a frequency of about 1550 MHz, but the frequency of the Montgomery multiplier (which uses a single 16*16 multiplier three times) is reduced to almost 500 MHz when the three multiplications are

Counter with push button switch design using VHDL and Xilinx

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问题 I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE. I want to design a very simple counter with the following inputs: Direction Count The count input will be assigned to a button and I want the counter to count up or down according to direction input when the button is pressed. I have written a sample VHDL before this one. It had a clock input and It was counting according to the clock input. Now I want it to count when I press the button instead of counting

How to debug a C program using SDK on xilinx?

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问题 I'm using an Atlys spartan 6 xc6slx45 ,I have to debug this code : 1-#include "stdio.h" 2-int main (void) 3-{ 4-// Initialization of the necessary variables 5-int i,j,k; 6-// Initialization of source A and B 4x4 matrices and result C matrix 7-int a[4][4]={ {1,2,3,4}, 8-{1,2,3,4}, 9-{1,2,3,4}, 10-{1,2,3,4}}; 11-int b[8][8]={ {1,2,3,4}, 12-{1,2,3,4}, 13-{1,2,3,4}, 14-{1,2,3,4}}; 15-int c[8][8]={ {0,0,0,0}, 16-{0,0,0,0}, 17-{0,0,0,0}, 18-{0,0,0,0}}; 19-xil_printf("‐‐ Entering main() ‐‐\r\n"); 20

Can Vivado handle user defined physical types?

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问题 I wrote some cross platform VHDL libraries for Xilinx XST, iSim, Altera Quartus II, Mentor Graphics QuestaSim and GHDL. Now I wanted to port my ISE 14.7 project, which uses these libraries to Vivado 2014.4, but one library seems to have fatal problems. My library physical defines several new user defined physical types like: FREQUENCY and BAUD ; conversion functions and report functions. One main use case is the calculation of delay or counter cycles for a given delay and system frequency. So

Can't receive UDP packet in Python

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问题 I'm having trouble receiving a UDP packet sent from an FPGA in a python program. I've checked similar questions and did the following: Checked that Wireshark can the see UDP packet Disabled windows firewall in PC Used sock.bind() since it's UDP packets Manually set the destination MAC address on Ethernet frame since FPGA does not support ARP Set dest IP to broadcast 10.10.255.255 for testing, no packets received Set the UDP checksum of the packet from the sender to 0x0000 Here's the python

During implementing FIFO buffer code for serial communication taking too much time

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问题 I am a new bee in VHDL coding. I am currently working on starter kit spartan 3e. I have written a code for transmitting 5 bytes to PC and receiving 4 bytes. Now I have to add fifo buffer before transmitting and after receiving bytes.I have written code( taken from Pong P Chu) also but not working. Its taking too much time for synthesis. Please tell me where I am going wrong. Thanks in advance. entity fifo is generic ( B : natural :=32; ---------------------------------------------------

Generating a pure sine wave as output form FPGA using VHDL code

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问题 We know that the output of an FPGA is digital but can we genrate a pure analog sine wave using a vhdl code. also can I specify the frequency of the sine wav. 回答1: Define "pure" - how many "bits" of quantisation can you live with... and what frequency? For lowish frequencies at lowish bits you could build a simple PWM or delta-sigma DAC in the FPGA and put a low-pass filter on the "outside" (sorry, that'll have to be real analogue hardware :) . This example may be informative Not going to get

嵌入式开发的四大职业发展方向，仅供参考

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【推荐】2019 Java 开发者跳槽指南.pdf(吐血整理) >>> 近几年来，随着移动互联网、物联网的迅猛发展，嵌入式技术日渐普及，在通讯、网络、工控、医疗、电子等领域发挥着越来越重要的作用;随着嵌入式技术及相关产品不断渗透到人们日常生活，大大小小公司对于嵌入式开发人才招聘需求猛增。介绍嵌入式开发职业发展方向之前，先了解一下嵌入式设备的本质。嵌入式设备的本质就是一台专用的、微型计算机，所以就像计算机一样由三个层次的东西组成： 1)硬件，包括cpu(如ARM)、存储(如flash)、I/O(显示模块、通讯模块、视音频模块、I/O控制电路等)。 2)系统级软件，主要是操作系统也就是OS，以及I/O软件如LCD、蓝牙、wifi、CDMA、声音等子系统。 3)应用软件，如基于linux的应用开发，基于Android的应用开发，基于iOS的应用开发等。事实上，所有带有数字接口的设备，大到飞机火箭，小到手机，电脑，甚至组成普通PC终端设备的键盘、鼠标、硬盘，目前市场上各种智能硬件产品等都使用嵌入式系统。嵌入式系统是将先进的计算机技术、半导体技术和电子技术和各个行业的具体应用相结合后的产物。嵌入式系统无疑是当前最热门最有发展前途的 IT应用领域之一。嵌入式开发的发展方向有很多，门槛高低不一样。下面主要介绍四大职业发展方向： ARM + Linux/Android开发据统计，全世界99