fpga | 易学教程

HOW do I write from a Spartan6 to the Micron external Cellular RAM on the Nexys3 FPGA Board?

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问题 I have looked everywhere, the datasheet, the Xilinx website, digilent, etc. etc. and can't find anything! I was able to use the Adept tool to verify that my Cellular RAM is functioning correctly, but I just can't find any stock VHDL code as a controller to write data to and read data from it!! Help!! 回答1: Found this link but it's for asynchronous mode, which is not nearly fast enough: http://embsi.blogspot.com/2013/01/how-to-use-cellular-ram-from-micron.html Eventually found this on the Nexys

BRAM_INIT in VHDL

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问题 I am simulating a processor based design where the program memory contents are held in a BRAM. I am realizing the program memory using VHDL (inferring BRAMs). I am trying to avoid CoreGen because I want to keep the design portable. Eventually this design will go to an FPGA. I am looking to see if there is a way to initialize memory contents of the BRAMs using VHDL generics ? I understand that Coregen uses COE file to initialize the BRAM but do we have a VHDL code based way to do this ? Let me

Vivado_hls 2014.4 Ubuntu 14.04 x64 vivado includes error

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问题 I am running Vivado HLS 2014.4 (x64) on Ubuntu 14.04 x64. Everything works in Vivado HLS 2012. In Vivado HLS 2014.4 GUI and Synthesis works but compilation of testbench does not. I am getting thousands of errors like this: Building file: /home/nic30/vivado/tb_axis_test.cpp Invoking: GCC C++ Compiler g++ -DAESL_TB -D__llvm__ -D__kernel -D__global -Dglobal -Dlocal -D__local -Dconstant -D__constant -Dprivate -D__private -D__private -I/opt/Xilinx/Vivado_HLS/2014.4/include/ap_sysc -I/opt/Xilinx

Can't infer register for … at … because it does not hold its value outside the clock edge

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问题 This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's worth. The actual error is: "Can't infer register for "spiclk_out" at [file] [line] because it does not hold its value outside the clock edge" ENTITY spi_state_machine IS PORT( spiclk_internal : IN STD_LOGIC; reset : IN STD_LOGIC; spiclk_out : BUFFER

Resolve multiple constant drivers for net Error

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问题 I do have following VHDL code example: LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY Test IS PORT ( Nios_Reset_n : IN STD_LOGIC; UserLed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END Test; ARCHITECTURE bdf_type OF Test IS COMPONENT misc PORT( reset_reset_n : IN STD_LOGIC; userleds_external_connection_export : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; BEGIN b2v_M1 : misc PORT MAP( reset_reset_n => Nios_Reset_n, userleds_external_connection_export => UserLed); UserLed(0)

Reconfiguration of FPGA in ML605 Board

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问题 The aim of my project is to load 3 bitstreams into the PROM; according to our requirement we load the 1or second or 3 bit file. The way i approached to the problem statement is : Initially I have taken 2 trigger inputs, depending on it the 2 or 3 bit file will be loaded.. as the default one would be the First bit file (User Logic). USER LOGIC : Explanation First I have instantiated the ICAP Virtex 6 primitive, secondly, I have written a State machine in which I'm sending few IPROGRAM command

How to find connected object in a binary image in VIVADO HLS?

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问题 I have a thresholded binary image as shown below: I want to find all connected object in the image. The code will take an input image stream and gives no. of connected components as output. I have already implemented it in C where matrices are stored and can be accessed directly by A[][] format. But in HLS images come in as a stream, which I have converted in hls::Mat . I am not sure whether I can perform an element-wise operation on Mat and whether mat is available for offline operations

Instantiation of RAM in FPGAs using VHDL

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问题 I was attempting to implement a dual port RAM as guided in this excellent blog post. However, ModelSim is giving the following warning when compiling: ** Warning: fifo_ram.vhdl(24): (vcom-1236) Shared variables must be of a protected type. I also seem unable to create this as a wave, indicating to me that the variable is not being recognised using my code below. How can I correctly declare this variable as a "protected" type? Also, as a more general question about shared variables - is this

FPGA学习及设计中的注意事项

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FPGA 学习及设计中的注意事项 1. 基础问题　　 FPGA 的基础就是数字电路和 HDL 语言，想学好 FPGA 的人，建议床头都有一本数字电路的书，不管是哪个版本的，这个是基础，多了解也有助于形成硬件设计的思想。在语言方面，建议初学者学习 Verilog 语言， VHDL 语言语法规范严格，调试起来很慢， Verilog 语言容易上手，而且，一般大型企业都是用 Verilog 语言。　　 2.EDA 工具问题　　熟悉几个常用的就可以的，开发环境 QuartusII ，或 ISE 就可以了，这两个基本是相通的，会了哪一个，另外的那个也就很 Easy 了。功能仿真建议使用 Modelsim ，如果你是做芯片的，就可以学学别的仿真工具，做 FPGA 的， Modelsim 就足够了。综合工具一般用 Synplify ，初学先不用太关心这个，用 Quartus 综合就 OK 了。　　 3. 硬件设计思想问题　　对于初学者，特别是从软件转过来的，设计的程序既费资源又速度慢，而且很有可能综合不了，这就要求我们熟悉一些固定模块的写法，可综合的模块很多书上都有，语言介绍上都有，不要想当然的用软件的思想去写硬件。　　 4. 学习习惯问题　　 FPGA 学习要多练习，多仿真， signaltapII 是很好的工具，可以看到每个信号的真实值，建议初学者一定要自己多动手

Receive an high rate of UDP packets with python

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问题 I'm working with python in order to receive a stream of UDP packets from an FPGA, trying to lose as few packets as possible. The packet rate goes from around 5kHz up to some MHz and we want to take data in a specific time window (acq_time in the code). We have this code now: BUFSIZE=4096 dataSock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) dataSock.settimeout(0.1) dataSock.bind((self.HOST_IP, self.HOST_PORT)) time0=time.time() data_list = [] while time.time()-time0<acq_time: fast