fpga | 易学教程

Solving Metastability Using Double-Register Approach

阅读更多关于 Solving Metastability Using Double-Register Approach

问题 For solving metastability caused by different clock domains in Verilog, double-register method is used. But as far as I know, the final output of metastability is undetermined. Output is independent of input. So, my question is how to guarantee the correctness of output using double-register method? Thanks. 回答1: You cannot be completely sure that you avoided metastability. As you mentioned, the output of a metastable flip-flop is unpredictable so you can potentially propagate a wrong value

How can I calculate propagation delay through series of combinational circuits using Verilog and FPGA?

阅读更多关于 How can I calculate propagation delay through series of combinational circuits using Verilog and FPGA?

问题 I'm new to FPGA and HDL but I'm trying to learn and cant figure this out. How can I calculate or estimate propagation delay though several levels of combination logic. Can I only determine this empirically or can I figure it out at design time. In this situation I'm using and FPGA to implement a parity setting and checking circuit. The circuit would look like a tree network of xor gates like the example pictures, except I intent xor 16 registers so there will be more levels or xor operations.

vhdl-ultrasonic sensor(hc-sr04)

阅读更多关于 vhdl-ultrasonic sensor(hc-sr04)

问题 I have a project. In my project, I am creating a car that keeps the distance between anything next to the car and the car itself. But, coding is a headache for me. I created 3 different project, and all of them seemed to me okay. Yet none of them worked in practice. Then, I created this code(the most basic one to understand-- no component at all). The sensor need 10 us pulse and waits for new pulse for 100ms. When I send the trigger signal, sensor responses and sends a ultrasonic wave. While

How do I debug Verilog code where simulation functions as intended, but implementation doesn't?

阅读更多关于 How do I debug Verilog code where simulation functions as intended, but implementation doesn't?

问题 I'm a bit stumped. I have a fairly large verilog module that I've tested in Simulation (iSim) and it functions as I want. Now I've hooked up it up in real life to another device using SPI, and some stuff works, and some stuff doesn't. For example, I can send a value using command A, and verify that the right value was received using command B. Works no problem. But if I send a value using command C, I cannot verify that it was received using command D. In simulation it works fine, so I feel I

Bitshifting std_logic_vector while keep precision and conversion to signed

阅读更多关于 Bitshifting std_logic_vector while keep precision and conversion to signed

问题 In VHDL I want to take a 14 bit input and append '00' on the end to give me a 16 bit number which is the 14 bit input multiplied by 4 and then put this into a 17 bit signed variable such that it is positive (the input is always positive). How should I go about this? like this? shiftedInput <= to_signed('0' & input & '00', 17); Or maybe like this? shiftedInput <= to_signed(input sll 2, 17); Or this? shiftedInput <= to_signed(input & '00', 17); Does it see that the std_logic_vector it's getting

verilog $readmemh takes too much time for 50x50 pixel rgb image

阅读更多关于 verilog $readmemh takes too much time for 50x50 pixel rgb image

问题 I am trying to compile a verilog code for FPGA programming where I will implement a VGA application. I use QuartusII and Altera. I am trying to use readmemh properly for acquiring a picture pixel by pixel. For now, I have converted a picture into rgb texts using matlab. Each has the following format and nothing else (example): 03 A0 15 B7 ... At the moment I am not getting any syntax errors however I had to define three registers each having 50x50 = 2500 bits and it is compiling quite slower,

mmap EINVAL error on UIO device

阅读更多关于 mmap EINVAL error on UIO device

I have trouble mapping physical memory on Xilinx Zynq after attempting to use UIO instead of mapping directly /dev/mem . While the plan is to run the application as a normal user instead of root this is still being run as root . Apparently the first mapping is successful while the rest done to the same file descriptor 12 ( /dev/uio/ps2pl ) fail. While the obvious difference is the offset, it is within the range (see device tree) and it is properly page aligned. This application was working well with /dev/mem . The error observed by running with strace is: open("/dev/uio/ps2pl", O_RDWR|O_SYNC)

Do bitwise operations distribute over addition?

阅读更多关于 Do bitwise operations distribute over addition?

问题 I'm looking at an algorithm I'm trying to optimize, and it's basically a lot of bit twiddling, followed by some additions in a tight feedback. If I could use carry-save addition for the adders, it would really help me speed things up, but I'm not sure if I can distribute the operations over the addition. Specifically if I represent: a = sa+ca (state + carry) b = sb+cb can I represent (a >>> r) in terms of s and c? How about a | b and a & b? 回答1: Think about it... sa = 1 ca = 1 sb = 1 cb = 1 a

Generating random integer in vhdl

阅读更多关于 Generating random integer in vhdl

问题 I need to generate a random integer between 0 - 1023 in vhdl however I couldn't find a good resource for this on the internet. Is there anyone help me please ? 回答1: Below is an example for generation of integers in range [0 : 1023] with uniform (even) distribution. Note that the floor operation must be used after multiplication with the max value + 1, in this case 1023 + 1 = 1024, in order to ensure uniform (even) distribution of all integer values in [0 : 1023], since using integer without

Seven Segment Multiplexing on Basys2

阅读更多关于 Seven Segment Multiplexing on Basys2

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four digit seven segment display on a BASYS2 board. I have checked to make sure that 0 enables the signal and that I have the ports mapped correctly. I believe the error is within my multiplexing logic since I am only able to display a single digit. I'm new to Verilog (am used to C) and would appreciate any suggestions. Thanks `timescale 1ns / 1ps module main (clock, AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE, CF, CG, CDP); //USED FOR SEVEN SEG input clock; output AN0, AN1, AN2, AN3, CA, CB, CC, CD, CE,