fpga

TAP (Test Anything Protocol) module for Verilog or SystemVerilog

假装没事ソ 提交于 2019-12-06 12:43:35
问题 Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time. 10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is()

Best way to convert for-loops into an FPGA

橙三吉。 提交于 2019-12-06 11:25:22
I am having trouble wrapping my head how to best replicate some C code in an FPGA using a for-loop (not my first time being stuck on this). The snippet of C code look like this: dot_product(&corr_sum, &sample_data_buffer[sample_index+d_circ_buf_size-sync_pattern_size], &sync_pattern[0], sync_pattern_size); abs_corr_sum += abs(corr_sum); Pretty straightforward, it is taking the dot product of two complex vectors and doing a cumulative sum of it. And he was my attempt to replicate it: always @(sample_index) begin // for each incoming sample abs_corr_sum = 64'd0; corr_sum = 64'd0; for (index2 = 0

What does “others=>'0'” mean in an assignment statement?

≡放荡痞女 提交于 2019-12-06 07:30:27
问题 cmd_register: process (rst_n, clk) begin if (rst_n='0') then cmd_r<= (others=>'0'); elsif (clk'event and clk='1') then cmd_r<=...; end if; end process cmd_register; I know "<=" specifies assignment but what is others ? And what does => do? 回答1: cmd_r is defined as a std_logic_vector , or unsigned or signed signal. let's see how this signal type are defined: type std_logic_vector is array (natural range <>) of std_logic; type unsigned is array (natural range <>) of std_logic; type signed is

VHDL - Incrementing Register Value on Push Button Event

落爺英雄遲暮 提交于 2019-12-06 07:01:14
I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0); do : out unsigned(7 downto 0) ); end raminfr; architecture rtl of raminfr is type ram_type is array (0

VHDL and FPGA's

倾然丶 夕夏残阳落幕 提交于 2019-12-06 04:19:40
I'm relatively new to the FPGA sceen and was looking to get experience with them and VHDL. I'm not quite sure what the benefit would be over using a standard MCU but looking for experience since many companies are looking for it. What would be a good platform to start out on and get experience for not to much money. Ive been looking and all I can find are 200 - 300 dollar boards if not 1000's. What should one look for in an FPGA development board, I hear high speed peripheral interfaces, and what I guess I'm really confused about is that an MCU dev board with around 50/100 GPIO can go for

Time stamp in VHDL

和自甴很熟 提交于 2019-12-06 03:31:20
问题 is there any function in VHDL which is used to get current simulation time at which a process is running? May be same like the function in systemC sc_time_stamp() 回答1: Yes there is. Use the keyword now . You can print the simulation time using VHDL Attributes: report "current time = " & time'image(now); You can also store the current time to a variable: variable v_TIME : time := 0 ns; v_TIME := now; -- STUFF HAPPENS v_TIME := now - V_TIME; --used to find delta time 回答2: If you want to know

Instantiation of RAM in FPGAs using VHDL

懵懂的女人 提交于 2019-12-06 03:30:53
I was attempting to implement a dual port RAM as guided in this excellent blog post . However, ModelSim is giving the following warning when compiling: ** Warning: fifo_ram.vhdl(24): (vcom-1236) Shared variables must be of a protected type. I also seem unable to create this as a wave, indicating to me that the variable is not being recognised using my code below. How can I correctly declare this variable as a "protected" type? Also, as a more general question about shared variables - is this variable shared between all entities in a design? library ieee; use ieee.std_logic_1164.all; use ieee

Incrementing a counter variable in verilog: combinational or sequential

耗尽温柔 提交于 2019-12-05 20:36:58
I am implementing an FSM controller for a datapath circuit. The controller increments a counter internally. When I simulated the program below, the counter was never updated. reg[3:0] counter; //incrementing counter in combinational block counter = counter + 4'b1; However, on creating an extra variable, counter_next, as described in Verilog Best Practice - Incrementing a variable and incrementing the counter only in the sequential block, the counter gets incremented. reg[3:0] counter, counter_next; //sequential block always @(posedge clk) counter <= counter_next; //combinational block counter

FPGA 第一个工程 -- LED控制

僤鯓⒐⒋嵵緔 提交于 2019-12-05 20:02:22
第一次接触新东西的时候,难免会磕磕碰碰,不过遇到问题不要着急,慢慢来。原因总归是我们自己引起的,一步步找到问题的根源,然后彻底解决它,避免下次再犯。 好了,进入正题 开发环境:Quartus II 15.0.0.145 64Bit FPGA芯片:EP4CE6E22C8N 第一步:创建工程 打开Quartus II软件,选择 File->New Project Wizard,如下图: 直接Next下一步 下面选择创建一个空的工程 工程创建完毕,接下来就是添加代码文件,在菜单栏选择 File->New 这里我选择的是Verilog HDL语言,文件创建完成后,向文件中添加代码,并保存。注意:保存的时候文件名必须和工程名一致。我们都知道在单片机中程序入口函数是main函数,但是Quartus II不一样,在Quartus II的工程中必须要有一个顶层设计文件,并且顶层设计文件中的模块名必须和工程名一致,顶层设计文件名也必须和工程名一致,而这个顶层设计文件中和工程同名的模块就是程序入口。 问:OK,至此可以编译了吗? 答:No!No!No!还没结束。 在单片机中要控制LED就必须要指定IO,并初始化IO,在这里IO不需要我们去初始化,我们只要指定就好了。 使用快捷键 Ctrl + Shift + N 打开引脚分配窗口,或者菜单栏 Assignments -> Pin Planner

fpga和单片机和arm和dsp的区别

不羁岁月 提交于 2019-12-05 17:46:56
fpga主要负责的是: FPGA 它的结构是查找表结构,其程序不用去太考虑芯片的结构,要注意的是时序上问题, 它的结构比较复杂,功能也很强大,一般应用在通信领域等比较高端的场合,FPGA更偏向于硬件电路 FPGA由于是硬件电路,运行速度直接取决于晶振速度,系统稳定,特别适合高速接口电路。 FPGA是用来设计芯片的芯片 单片机: 单片机是一种微处理器,类似于电脑CPU的,它一般采用的是哈佛总线结构,或者冯诺依曼结构, 对单片机的编程很大程度上要考虑到它的结构和各个寄存器的作用,单片机用途比较广,一般用在控制流水线上 单片机是没有系统的,单片机是一个微控制器,通过加载模块软件来实现某种功能,单片机是成型的芯片 arm:arm可以说是单片机的一种,但arm的ROM和RAM远大于单片机, 而且IO口功能和处理速度也是两个级别的,arm能上很多操作系统,所以arm常用来开发手机等多媒体产品 DSP: DSP是TI首创的数字信号处理器,主要是进行数字信号的处理和运算的,主频很高,有硬件乘法器,做FFT啊就很简单迅速, 是一种独特的微处理器,有自己的完整指令系统,是以数字信号来处理大量信息的器件。 一个数字信号处理器在一块不大的芯片内包括有控制单元、运算单元、各种寄存器以及一定数量的存储单元等等 DSP还有一个特色就是对一些特殊算法的支持如快速福利叶变换等