Time stamp in VHDL

问题

is there any function in VHDL which is used to get current simulation time at which a process is running? May be same like the function in systemC sc_time_stamp()

回答1:

Yes there is. Use the keyword now.

You can print the simulation time using VHDL Attributes:

report "current time = " & time'image(now);

You can also store the current time to a variable:

variable v_TIME : time := 0 ns;
v_TIME := now;
-- STUFF HAPPENS
v_TIME := now - V_TIME; --used to find delta time

回答2:

If you want to know the time within your synthesised design, you will have to manage that yourself. For example, a free-running counter clocked from the same clock as the rest of your logic can be used to capture the time of particular events into registers. You could then transfer those registers periodically over some interface to a host PC or similar, or use an embedded logic analyser.

now is a purely simulation only construct, which tells you the simulation time to whatever resolution the simulator is set to. The real hardware has no concept of real time, only clock cycles, and has no standardised interface for accessing a console, so being able to synthesise report time'image(now) is not even remotely an option.

来源：https://stackoverflow.com/questions/20355021/time-stamp-in-vhdl